J
Jerzy Tyszer
Researcher at Poznań University of Technology
Publications - 177
Citations - 5555
Jerzy Tyszer is an academic researcher from Poznań University of Technology. The author has contributed to research in topics: Test compression & Automatic test pattern generation. The author has an hindex of 40, co-authored 170 publications receiving 5321 citations. Previous affiliations of Jerzy Tyszer include Siemens & Mentor Graphics.
Papers
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Journal ArticleDOI
Embedded deterministic test
TL;DR: This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time.
Proceedings ArticleDOI
Embedded deterministic test for low cost manufacturing test
Janusz Rajski,Jerzy Tyszer,M. Kassab,Nilanjan Mukherjee,Rob Thompson,Kun-Han Tsai,A. Hertwig,Nagesh Tamarapalli,Grzegorz Mrugalski,Geir Eide,Jun Qian +10 more
TL;DR: Embedded deterministic test technology is introduced, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time.
Proceedings ArticleDOI
Convolutional compaction of test responses
TL;DR: A finite memory compactor called convolutional compactor that provides compaction ratios of test responses in excess of 100x even for a very small number of outputs and the capability to detect multiple errors, handling of unknown states, and the ability to diagnose failing scan cells directly from compacted responses is introduced.
Patent
Arithmetic built-in self-test of multiple scan-based integrated circuits
Janusz Rajski,Jerzy Tyszer +1 more
TL;DR: In this paper, an ABIST of a number of peripheral devices having parallel scan registers coupled to a processor core, all within an integrated circuit, is presented, where operating logic generates pseudo-random test patterns for the peripheral devices using a mixed congruential generation scheme.
Patent
Test pattern compression for an integrated circuit test environment
TL;DR: In this paper, a method for compressing test patterns to be applied to scan chains in a circuit under test is presented, which includes generating symbolic expressions associated with scan cells within the scan chains.