Test Compression ratios are currently stalled at 100–200X. A new 2-dimensional physically-aware sequential Compressor-Decompressor design addresses the severe wiring congestion as well as the test coverage droop and pattern spike at the highest compression ratios. Results on some commonly used industrial designs shows a 2X reduction in routing overhead and congestion associated with Test Compression logic. The target test coverage is maintained while achieving up to 3.7X reduction in test data volume and test application time beyond the conventional methods.

Advancing test compression to the physical dimension

As chip design sizes continue to increase and they contain multiple instances of large and small cores, there is a need for a chip test architecture that allows efficient chip-level tests to be created while also reducing the memory and CPU time needed to create the tests. We define a hierarchical and core-based architecture for generating tests for cores and migrating them to the chip. This architecture allows testing multiple instances of the same core for the same cost as testing a single instance. The architecture also allows testing multiple instances of different cores as well. Memory use is kept low by generating tests for cores out of context and migrating them to the chip. We never have to build a full gate-level chip ATPG model. We show results of pattern count reduction possible when targeting multiple cores simultaneously.

Efficient testing of hierarchical core-based SOCs

Modern large SoC designs typically have many cores. Each core requires a certain number of input / output test channels. At the chip level, however, the total number of test channels is limited such that all core-level test channels cannot be accessed at the same time. One solution to this problem is obviously using hierarchical pattern retargeting, where cores can be wrapped and tested individually. Another solution is to use channel sharing / channel broadcasting. The first solution is scalable and good for very large designs. The second solution is good for medium-sized designs that can still run ATPG at the chip level. In this paper, we would like to share our SoC testing experience with one medium-sized case and using channel sharing / broadcasting methodology. Experimental results show that with the proposed SoC test methodology, the total test time can be reduced up to about 2X.

Case Study of Testing a SoC Design with Mixed EDT Channel Sharing and Channel Broadcasting

System-on-Chip (SoC) designs are increasingly difficult to test using traditional scan access methods without incurring inefficient test time, high planning effort, and physical design/timing closure challenges. The number of cores keeps growing while chip pin counts available for scan remain constant or decline, limiting the ability to drive cores concurrently. With increasingly commonplace tiling and abutment, the scan distribution hardware must be placed inside the cores, making balanced pipelining when broadcasting to identical cores difficult. optimizing test time requires analyzing all the cores and subsequently changing the test hardware in the cores. Internal shift speed constraints may limit the ability to shift data in and out of the chip at high rates. Differences in pattern counts or scan chain lengths between cores tested in parallel can result in padding and increased test time. SSN is a bus-based scan data distribution architecture designed to address all these challenges. It enables simultaneous testing of any number of cores even with few chip I/Os. It facilitates short test time by enabling high-speed data distribution, by efficiently handling imbalances between cores, and by supporting testing of any number of identical cores with a constant cost. It provides a plug-and-play interface in each core that is well suited for abutted tiles, and simplifies scan timing closure. This paper also compares the test cost and implementation productivity of SSN with those of Intel’s Structural Test Fabric.

Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs

Scan test data compression is widely used in industry to reduce test data volume (TDV) and test application time (TAT). This paper shows how multiple scan chain expansion ratios can help to obtain high test data compression in system-on-chips. Scan chains are partitioned with a higher expansion ratio than normal in scan compression mode and then are gradually concatenated based on a cost function to detect any faults that could not be detected at the higher expansion ratios. It improves the overall test compression ratio since it potentially allows faults to be detected at the highest expansion ratio. This paper introduces a new cost function to choose scan chain concatenation candidates for concatenation for multiple expansion ratios. To avoid TDV and TAT increase by scan concatenation, the proposed method takes a logic structure and scan chain length into consideration. Experiment results show the proposed method reduces TAT and TDV by 53%–64% compared with a traditional scan compression method.

Enhancing Test Compression With Dependency Analysis for Multiple Expansion Ratios

The paper discusses practical issues involved in applying scan bandwidth management to large industrial system-on-chip (SoC) designs deploying embedded test data compression. These designs pose significant challenges to the channel bandwidth management methodology itself, flow, and tools. The paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with EDT-based test data compression. Moreover, some recently proposed SoC test scheduling algorithms are refined accordingly by making provision for (1) setting up test configurations minimizing test time, (2) optimization of SoC pin allocation based on scan data volume, and (3) handling physical constraints in realistic applications. Detailed presentation of a case study is illustrated with a variety of experiments that allow one to learn how to tradeoff different architectures and test scheduling.

EDT bandwidth management - Practical scenarios for large SoC designs

Modern SOCs may be composed of hundreds of individual physical modules, referred to as tiles. The total number of scan channels servicing these tiles often greatly exceeds the number of SOC device pins available to connect those channels to test equipment. Traditional reliance on a small number of pin-to-channel test mode configurations, predetermined in hardware, results in inefficient scan data bandwidth utilization. Herein is presented a flexible switching network called the Scan Routing Fabric (SRF) which can connect any set of tiles' scan channels to available SOC pins in order to facilitate optimal scheduling of tile patterns by box-packing algorithms. Other planned improvements to be integrated with the SRF, such as MICTAM, and independent mode are also discussed. Results from deployment on the latest AMD chip show a one-third reduction in test time.

Maximizing scan pin and bandwidth utilization with a scan routing fabric

Modern SOCs may be composed of hundreds of individual physical modules, referred to as tiles. The total number of scan channels servicing these tiles often greatly exceeds the number of SOC device pins available to connect those channels to test equipment. Traditional reliance on a small number of pin-to-channel test mode configurations, predetermined in hardware, results in inefficient scan data bandwidth utilization. Herein is presented a flexible switching network called the Scan Routing Fabric (SRF) which can connect any set of tiles' scan channels to available SOC pins in order to facilitate optimal scheduling of tile patterns by bin-packing algorithms. Other planned improvements to be integrated with the SRF, such as dynamic bandwidth management, MICTAM, and independent mode are also discussed.

Toward more efficient scan data bandwidth utilization on modern SOCs

SQL is a widely adopted programming language for relational databases. Its ability to concisely process data sets makes it suitable as a complementary construct for data analysis in general-purpose programming languages. This work presents SelectML , which inte-grates the Select Query capabilities directly into the Ocaml language, where a query is a first-class language construct. Query expressions are in declarative syntax, where programmers can perform filtering, ordering, and grouping operations on data sets with a minimum of code. SelectML retrofits the queries into pure OCaml, based on the formally defined translation schema. Our implementation allows SelectML to be a flexible framework for customizing the types of inputs, outputs and operations of the queries. SelectML deploys query plan optimizations to make query executions more efficient. We also discuss the potential of connecting to databases from SelectML .

Yan Dong

Papers

EDT bandwidth management - Practical scenarios for large SoC designs

Maximizing scan pin and bandwidth utilization with a scan routing fabric

Toward more efficient scan data bandwidth utilization on modern SOCs

An SQL Frontend on top of OCaml for Data Analysis