This paper describes the design and optimization of VCOs with quadrature outputs. Systematic design of fully integrated LC-VCOs with a high inductance tank leads to a cross-coupled double core LC-VCO as the optimal solution in terms of power consumption. Furthermore, a novel fully differential frequency tuning concept is introduced to ease high integration. The concepts are verified with a 0.25-/spl mu/m standard CMOS fully integrated quadrature VCO for zero- or low-IF DCS1800, DECT, or GSM receivers. At 2.5-V power supply voltage and a total power dissipation of 20 mW, the quadrature VCO features a worst-case phase noise of -143 dBc/Hz at 3-MHz frequency offset over the tuning range. The oscillator is tuned from 1.71 to 1.99 GHz through a differential nMOS/pMOS varactor input.

/pdf/low-power-low-phase-noise-differentially-tuned-quadrature-q31y9qihqr.pdf

Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS

Improved apparatus for a radio communication system having a multiplicity of mobile transceiver units selectively in communication with a plurality of base transceiver units which, in turn, communicate with one or more host computers for storage and manipulation of data collected by bar code scanners or other collection means associated with the mobile transceiver units. A network controller and an adapter which has a simulcast and sequential mode provide selective interface between host computers and base transceivers. A scheme for routing data through the communication system is also disclosed wherein the intermediate base stations are organized into an optimal spanning-tree network to control the routing of data to and from the RF terminals and the host computer efficiently and dynamically. Additionally, redundant network and communication protocol is disclosed wherein the network utilizes a polling communication protocol which, under heavy loaded conditions, requires that a roaming terminal wishing to initiate communication must first determine that the channel is truly clear by listing for an entire interpoll gap time. In a further embodiment, a criterion used by the roaming terminals for attaching to a given base station reduces conflicts in the overlapping RF regions of adjacent base stations.

Network supporting roaming, sleeping terminals

Measuring the dynamics of neural processing across time scales requires following the spiking of thousands of individual neurons over milliseconds and months. To address this need, we introduce the Neuropixels 2.0 probe together with newly designed analysis algorithms. The probe has more than 5000 sites and is miniaturized to facilitate chronic implants in small mammals and recording during unrestrained behavior. High-quality recordings over long time scales were reliably obtained in mice and rats in six laboratories. Improved site density and arrangement combined with newly created data processing methods enable automatic post hoc correction for brain movements, allowing recording from the same neurons for more than 2 months. These probes and algorithms enable stable recordings from thousands of sites during free behavior, even in small animals such as mice.

/pdf/neuropixels-2-0-a-miniaturized-high-density-probe-for-stable-1apgftfan8.pdf

Neuropixels 2.0: A miniaturized high-density probe for stable, long-term brain recordings

A local-oscillator phase-shifting approach is introduced to implement a fully integrated 24-GHz phased-array receiver using SiGe technology. Sixteen phases of the local oscillator are generated in one oscillator core, resulting in a raw beam-forming accuracy of 4 bits. These phases are distributed to all eight receiving paths of the array by a symmetric network. The appropriate phase for each path is selected using high-frequency analog multiplexers. The raw beam-steering resolution of the array is better than 10deg for a forward-looking angle, while the array spatial selectivity, without any amplitude correction, is better than 20 dB. The overall gain of the array is 61 dB, while the array improves the input signal-to-noise ratio by 9 dB

A 24-GHz SiGe phased-array receiver-LO phase-shifting approach

Silicon offers a new set of possibilities and challenges for RF, microwave, and millimeter-wave applications. While the high cutoff frequencies of the SiGe heterojunction bipolar transistors and the ever-shrinking feature sizes of MOSFETs hold a lot of promise, new design techniques need to be devised to deal with the realities of these technologies, such as low breakdown voltages, lossy substrates, low-Q passives, long interconnect parasitics, and high-frequency coupling issues. As an example of complete system integration in silicon, this paper presents the first fully integrated 24-GHz eight-element phased array receiver in 0.18-/spl mu/m silicon-germanium and the first fully integrated 24-GHz four-element phased array transmitter with integrated power amplifiers in 0.18-/spl mu/m CMOS. The transmitter and receiver are capable of beam forming and can be used for communication, ranging, positioning, and sensing applications.

/pdf/integrated-phased-array-systems-in-silicon-2i0prw8slb.pdf

Integrated Phased Array Systems in Silicon

List of Figures. List of Tables. List of Symbols and Abbreviations. Preface. 1. Introduction. 2. Phase-Locked Loop Frequency Synthesizers. 3. Voltage-Controlled Oscillator Phase Noise. 4. Bonding Wire Inductance VCOs. 5. Planar-Inductor VCOs. 6. High-Frequency CMOS Prescalers. 7. A Fully Integrated CMOS PLL Frequency Synthesizer. 8. General Conclusions. Bibliography. Index.

Wireless CMOS Frequency Synthesizer Design

Large-scale in vivo electrophysiology requires tools that enable simultaneous recording of multiple brain regions at single-neuron level. This calls for the design of more compact neural probes that offer even larger arrays of addressable sites and high channel counts. With this aim, we present in this paper a quad-shank approach to integrate as many as 5,120 sites on a single probe. Compact fully-differential recording channels were designed using a single-gain-stage neural amplifier with a 14-bit ADC, achieving a mean input-referred noise of 7.44 μVrms in the action-potential band and 7.65 μVrms in the local-field-potential band, a mean total harmonic distortion of 0.17% at 1 kHz and a mean input-referred offset of 169 μV. The probe base incorporates 384 channels with on-chip power management, reference-voltage generation and digital control, thus achieving the highest level of integration in a neural probe and excellent channel-to-channel uniformity. Therefore, no calibration or external circuitry are required to achieve the above-mentioned performance. With a total area of 2.2 × 8.67 mm2 and a power consumption of 36.5 mW, the presented probe enables full-system miniaturization for acute or chronic use in small rodents.

A Compact Quad-Shank CMOS Neural Probe With 5,120 Addressable Recording Sites and 384 Fully Differential Parallel Channels

A device and a method are presented for generating an intermitted oscillating signal comprising a plurality of oscillating portions separated from each other in time. The device and method are suited for communication systems, in particular for Ultra-Wide Bandwidth (UWB) applications. The device comprises a variable oscillator for generating the oscillating portions; switching circuitry for switching on/switching off the variable oscillator at the beginning/end of each oscillating portion; and circuitry for setting initial conditions in the variable oscillator to impose a predefined transient and a characterizing frequency upon each start-up.

Device and method for generating a signal with predefined transcient at start-up

A voltage controlled oscillator with automatic center frequency calibration. The frequency range of the oscillator is increased by switchable capacitor circuits which add or remove extra capacitors in parallel with the variable capacitor of the resonant circuit. Different voltage versus frequency characteristics are obtained. The switchable capacitor circuits are controlled by a detection circuit that sends a reset pulse to a feedback circuit of the VCO when a control voltage from the feedback circuit reaches predetermined low or high voltage limits of the characteristics. Upon reception of the reset pulse, the feedback circuit changes the control voltage from the reached limit into an intermediate voltage between the low and high voltage limits. The control voltage is reset in the middle of a voltage versus frequency characteristic onto which the output frequency is also centered. The VCO includes a selection circuit adapted to immediately change the value of the control voltage.

Voltage controlled oscillator with automatic center frequency calibration

Achieving high linearity and bandwidth with good power efficiency makes the design of ADCs in deep nanoscale CMOS processes very challenging, as the constraints of low-voltage operation and limited intrinsic gain often dictate the use of power-consuming analog circuits and intensive digital calibration. This paper addresses these problems by introducing a pipelined ADC that exploits the low but very constant open-loop gain versus output voltage characteristic of the ring amplifier (ringamp) to achieve both high speed and linearity in low-voltage nanoscale CMOS designs. A tunable ringamp biasing scheme using an anti-parallel arrangement of CMOS transistors and an active ringamp-based common-mode feedback are also introduced. A single-channel prototype ADC is implemented in a standard 28-nm CMOS process, achieving 58.7-dB SNDR and 72.4-dB SFDR at 600 MS/s while consuming 14.5 mW from a single 0.9-V supply, resulting in Walden and Schreier figure-of-merit (FoM) values of 34.4 fJ/conv.-step and 161.9 dB, respectively.

Jan Craninckx

Papers

Wireless CMOS Frequency Synthesizer Design

A Compact Quad-Shank CMOS Neural Probe With 5,120 Addressable Recording Sites and 384 Fully Differential Parallel Channels

Device and method for generating a signal with predefined transcient at start-up

Voltage controlled oscillator with automatic center frequency calibration

A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS