Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection. >

https://www-inst.eecs.berkeley.edu/~ee230/sp08/takagi%20universal%20mobility%20I%201994.pdf

On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Flash EEprom system

Two new epitaxial technologies have emerged in recent years (molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD)), which offer the promise of making highly advanced heterostructures routinely available. While many kinds of devices will benefit, the principal and first beneficiary will be bipolar transistors. The underlying central principle is the use of energy gap variations beside electric fields to control the forces acting on electrons and holes, separately and independently of each other. The resulting greater design freedom permits a re-optimization of doping levels and geometries, leading to higher speed devices. Microwave transistors with maximum oscillation frequencies above 100 GHz and digital switching transistors with switching times below 10 ps should become available. An inverted transistor strucure with a smaller collectors on top and a larger emitter on the bottom becomes possible, with speed advantages over the common "emitter-up" design. Double-heterostructure (DH) transistors with both wide-gap emitters and collectors offer additional advantages. They exhibit better performance under saturated operation. Their emitters and collectors may be interchanged by simply changing biasing conditions, greatly simplifying the architecture of bipolar IC's. Examples of heterostructure implementations of I2L and ECL are discussed. The present overwhelming dominance of the compound semiconductor device field by FET's is likely to come to an end, with bipolar devices assuming an at least equal role, and very likely a leading one.

/pdf/heterostructure-bipolar-transistors-and-integrated-circuits-1dm46dhqew.pdf

Heterostructure bipolar transistors and integrated circuits

A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.

Wear leveling techniques for flash EEPROM systems

Theory predicts appreciable bandgap narrowing in silicon for impurity concentrations greater than about 1017 cm−3. This effect influences strongly the electrical behaviour of silicon devices, particularly the minority carrier charge storage and the minority carrier current flow in heavily doped regions. The few experimental data known are from optical absorption measurements on uniformly doped silicon samples. New experiments in order to determine the bandgap in silicon are described here. The bipolar transistor itself is used as the vehicle for measuring the bandgap in the base. Results giving the bandgap narrowing (ΔVg0) as a function of the impurity concentration (N) in the base (in the range of 4.1015–2.5 1019 cm−3) are discussed. The experimental values of ΔVg0 as a function of N can be fitted by: δV g0 = V 1 ln N N 0 + ln 2 N N 0 +C where V1, N0 and C are constants. It is also shown how the effective intrinsic carrier concentration (nie) is related with the bandgap narrowing (ΔVg0).

Measurements of bandgap narrowing in Si bipolar transistors

In the literature, separate models exist for the apparent bandgap narrowing in n - and p -type Si, yielding a smaller bandgap narrowing in n -type than in p -type Si. Using a recently-published model, which describes both the majority and the minority carrier mobility, we have recalculated the apparent bandgap narrowing from the measurements upon which the bandgap narrowing models mentioned above are based. The results of this new interpretation show no difference in apparent bandgap narrowing in n - and p -type Si. A function describing the unified bandgap narrowing is presented.

Unified apparent bandgap narrowing in n- and p-type silicon

Optical absorption measurements [1] and theoretical calculations [2–9] have shown that the bandgap in silicon is not only temperature-dependent but is also influenced by the impurity concentration at higher values. Recent electrical measurements [10] of the pn-product in the base region of bipolar transistors made it possible to derive the bandgap narrowing quantitatively as a function of the impurity concentration.

In this paper it will be shown that theoretical calculation of the pn-product as a function of temperature and impurity concentration can be approximated by the following relationship: pn = nie2(N, T) = CT3 exp (− qVgo(N)/kT) for temperatures between about 280 and 450°K.

Moreover the calculated values for C and Vgo(N) show surprisingly good quantitative agreement with the values derived from the above mentioned pn-measurements [10].

The pn-product in silicon

A method for solving numerically the two-dimensional (2D) semiconductor steady-state transport equations is described. The principles of this method have been published earlier [1]. This paper discusses in detail the method and a number of considerable improvements. Poisson's equation and the two continuity equations are discretized on two networks of different rectangular meshes. The 2D continuity equations are approximated by a set of difference equations assuming that the hole and electron current density components along the meshlines are constant between two neighboring meshpoints in a way similar to that used by Gummel and Scharfetter [2] for the one-dimensional (1D) continuity equations. The resulting difference approximations have generally a much larger validity range than the conventional difference formulations where it is assumed that the change in electrostatic potential between two neighboring points is small compared with k T/q . Therefore, a much smaller number of meshpoints is necessary than for the conventional difference approximations. This reduces considerably the computation time and the required memory space. It will be shown that the matrix of the coefficients of this set of difference equations is always positive definite. This is an important property and guarantees convergence and stability of the numerical solution of the continuity equations. The way in which the difference approximations for the continuity equations are derived gives directly consistent expressions for the current densities that can be used for calculating the currents. In order to demonstrate the kind of solutions obtainable, steady-state results for a bipolar n-p-n silicon transistor are presented and discussed.

Computer-aided two-dimensional analysis of bipolar transistors

In small bipolar and MOS transistors, the electrons gain much less energy than according to the maximum electric field. This is due to nonlocal electron heating and the small width of the E-field peak. The simplified energy balance equation with the energy relaxation length lambda /sub e/ as parameter gives the electron temperature for a given electric field distribution. From a series of MBE (molecular beam epitaxy)-grown bipolar transistors and scaled submicron MOS transistors, lambda /sub e/=650 AA was found. With the calculated temperature distribution and known empirical models for the impact ionization, avalanche (substrate) currents are accurately predicted. This procedure can easily be implemented, as postprocessing, in existing device simulators with hardly any extra computation time. It extends in a consistent way the validity range of these simulators to future device generations. >

Jan W. Slotboom

Papers

Measurements of bandgap narrowing in Si bipolar transistors

Unified apparent bandgap narrowing in n- and p-type silicon

The pn-product in silicon

Computer-aided two-dimensional analysis of bipolar transistors

Non-local impact ionization in silicon devices