Showing papers by "Jean-Christophe Crebier published in 2009"

Diode-clamped multilevel converters with integrable gate-driver power-supply circuits

Abstract: Recent contributions in pulse width modulations (PWM) for multilevel diode-clamped converters enable the use of these converters with passive front-ends, any number of levels, and small dc-link capacitors. Highly compact converters designs based on these topologies can be envisioned. However, the design of the gate-driver power-supply for the multiple controlled semiconductor devices remains an important issue to be addressed. This paper focuses on the design of such circuits and the analysis of the resulting multilevel converter performance. A simple circuit connected across each power switch and monolithically integrable within it is selected. These circuits lead to simple, compact, and efficient converter designs. The main issues arising from the operation of the multilevel converter with such circuits are analyzed, and both hardware and software solutions are proposed. In particular, a new PWM strategy is presented. Experimental results are provided verifying the good performance of all proposed solutions.

Design of Modular Converters; Survey and Introduction to Generic Approaches

Abstract: This paper presents a new approach based on converter networks using elementary cells (ec). It deals with the beginning of research and development carried out on the design of the "ec", the random command and the magnetic coupling among the elementary cells. This paper introduces at first the recent works carried out on interleaved "ec" and power electronics converters (cvs) into networks: from basic interleaving approaches, trying to minimize filter sizes up to highly coupled solutions trying to optimize sizes but also current and voltage levels. In the next sections of the paper, the modular approach will be presented. The paper presents a study showing how a random mode control is used to simplify the implementation of a generic "ec" into any network. Evaluating the output voltage filtering criteria, we compare classical synchronous interleaved and random mode controls. Then, the paper focuses on the design and the characterization of the elementary cell and especially on its active part. The last part of the paper focuses on magnetic coupling for converter coupling and filtering. Experimental results underline the importance of coupling among elementary cells and inside the corresponding "cvs" and an analytical study of magnetic coupling is presented. An 2n-windings transformer formed of n identical three-winding transformers is used to connect the "ec" among them. The aims of these studies are to improve electrical management of modular "cvs" network without any constraints on the modularity and the genericity of the approach.

Implementation and analysis Of large winding ratio transformers

Abstract: The paper presents the work that has been carried out trying to improve the behavior and the performances of DC to DC step up converters with high conversion ratio. Especially, it is studied how the design and the realization of the magnetic HF transformer can be improved in order to increase the global efficiency of hard switch isolated DC to DC converters. It is shown that a split in conductors and then in magnetic core can be consedred to improve the performances of the converter. Practical realization and implementation are used to validate the approaches considered in this paper. Thermal imaging helps to conclude on the work. Especially, it is shown that new technological approaches, for the passive but also the active devices, lead to better operations. The important results of the work are the presentation of a simple and very effective way to design and to build HF magnetic transformers with high transformation ratios thanks to an original winding technique. The new transformer structure is named SSWT. The second important result coming from this work is that interleaved structures added to technology and design may bring interesting results from electrical and thermal point of views.

Design and realization of autonomous power CMOS single phase inverter and rectifier for low power conditioning applications

Abstract: This paper deals with the design, the realization and the characterization of an integrated converter for low voltage and low power, isolated applications (3.3 V, 1 W). It is based on the association of two generic silicon dies performing DC to AC and AC to DC operations. The power dies are designed in CMOS technology and operate at high frequency (1 MHz) and high efficiency. This high power density realization includes the power circuit and the control electronic. The integrated conversion structure can operate as an inverter or as a rectifier in a wide range of power flows and input voltages. Three important issues are addressed in this paper: design of the power part at high efficiency, reduced consumption of the control electronic and the gate drivers, and implementation with reduced parasitic behavior. The practical implementation and characterization are also addressed in a second part. First tests are carried out with packaged dies on PCB boards, in order to simplify the implementation. The efficiency of the inverter reaches up to 92% as a function of input voltage with these conditions. The second experimental investigation is a full DC to DC converter implemented with two CMOS power dies (one inverter and one rectifier) together with an HF transformer and an output LC filter. This article ends with the study of the packaging in order to minimize parasitics elements, such as resistances and inductances, which can be very harmful for the global efficiency of our micro-converter.

Electrical characterization of a pressed contact between a power chip and a metal electrode

Abstract: This study deals with the power electronics packaging and the needs for additional knowledge about electrical pressed contact behavior. For this, a measure bench has been realized. It is able to characterize the pressed interface between a metal electrode and a power chip as a function of the clamping force (0-8000N) and the temperature (up to 100°C). First measurement results show that the electrical contact resistance is negligible compared to the chip on-state voltage. Second measurement results show that the high value of the chip metallization resistance masks also the contact resistance. Finally, it appears that it is necessary to estimate the chip contact zone influences on the current repartition. Then a method based on both, the use of a chip model and the measurements directly on the chip, has been developed. It is able to look for the steady state current repartition in the chip as a function of the contact zone and the chip metallization physical parameters.

Complementary MOS structures for common mode EMI reduction

Abstract: The paper deals with the management and the reduction of conducted common mode EMI noise in power converters. Especially, it is presented how complementary P-N MOSFET structures, used in a specific manner, are able of great and natural common mode current reductions. The advantages obtained by the use of complementary MOSFET topologies are balanced with the additional conduction losses that P MOSFETs are responsible of. The paper presents these issues based on simulation and practical results.

Quantification of benefits and drawbacks in power conversion based on complementary MOS structures

Abstract: The paper deals with the advantages and drawbacks using complementary MOS structures in power converter. Approaching from the common mode conducted EMI perspective, the paper shows, at first, how beneficial the complementary structures are. Experimental and simulation results underline the specific behavior of such structures. Then, other advantages and also drawbacks are discussed and analyzed. This is made regarding the converter efficiency and the gate drivers operation for each converter leg. These issues are examined using simulations and experiments.