The reliability requirements of Flash memory become more and more challenging. Flash memory technology development needs test chips to allow large statistical studies and a product-like approach. In this paper, we present a methodology of bitmap analysis to extract and follow the intrinsic and extrinsic parameters of a 40nm eFlash technology during ramp-up. This methodology is, first, based on analog bitmap acquisition on 512kB test chip, followed by correction of spatial variabilities like peripheral circuits' influences, array organization impacts and process-induced effects, to extract supplementary cell electrical parameters such as threshold voltage, transconductance or programing window. Finally, such an analysis tool enhances the advantageous properties of a test chip, its large memory cell statistics and its product-like organization, to give more reliable data. It yields more information about intrinsic cell technology weaknesses and the best way to tackle them when integrated at product level.

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Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip

This paper presents a novel methodology to observe the leakage current origin in SiOC:H low-$\kappa$ intermetallic dielectric as well as a method to localise electrically the breakdown point in usual comb/serpentine/comb structures. Our results indicate that high leakage current is a consequence of a global moisture-induced SiOC:H dielectric modification and demonstrate that EMMI observations of such leakage current is possible. Besides, we have disclosed and validated a fast electrical breakdown localisation method fully compatible with automated test steps such as Parametric Test to track eventual weaknesses in reliability structures for instance.

Electrical and optical localisation of leakage current and breakdown point in SiOC:H low-k dielectrics

A new, cage-like structure is presented and is shown to be able to electrically identify a probe needle that has fallen slightly off its probe pad, even when the standard probe resistance structure (pads shorted together) reports “good” probe resistance. Using both structures together enables a more accurate evaluation of a probe system’s capabilities. Both test structures were used to compare three types of probe cards, reporting the smallest probe pad size that provides 100& probe yield. 

Test Structure for Evaluation of Pad Size for Wafer Probing

A new, cage-like structure is presented and is shown to be able to electrically identify a probe needle that has fallen slightly off its probe pad, even when the standard probe resistance structure (pads shorted together) reports “good” probe resistance. Using both structures together enables a more accurate evaluation of a probe system’s capabilities. Both test structures were used to compare three types of probe cards, reporting the smallest probe pad size that provides 100& probe yield.

This paper underlines the damages induced by probing on narrow pads reliability of specifically designed test structures placed on dicing streets and indicates that probing during electrical test steps provokes detrimental cracks diving from the passivation through the BEOL layers providing a path for moisture ingress.

Probing impact on pad moisture tightness: A challenge for pad size reduction

The impact of CMOS post nitridation annealing (PNA) temperature on a 40nm embedded Flash reliability is studied. Electrical characterizations of the Flash tunnel oxide are carried out on single cell. These are used to explain the better results in terms of endurance and data retention obtained on a 512kB test chip with a lower annealing temperature. This result can be linked with the decrease of nitrogen in the bulk oxide, improving oxide wear out performance against electrical stress and stress induced leakage current (SILC). The on-chip characterization is, here, an invaluable tool to show the extrinsic behavior in the memory array and apply product-like stress.

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Impact of CMOS post nitridation annealing on reliability of 40nm 512kB embedded Flash array

This paper presents an in depth study of the moisture influence on reliability and electrical characteristics of SiOC:H low-κ dielectric material. Firstly, TDDB models have been evaluated on material without moisture and Impact Damage model is found to be the most accurate for lifetime estimation. Then, various characterization techniques reveal that moisture provokes a significant decrease of the Time-to-breakdown (TBD) together with major modifications of conduction and breakdown mechanisms. Finally, results suggest that material polarizability modification might play a role in the evidenced premature breakdown.

Jean-Michel Moragues

Papers

Probing impact on pad moisture tightness: A challenge for pad size reduction

Impact of CMOS post nitridation annealing on reliability of 40nm 512kB embedded Flash array

Electrical and optical localisation of leakage current and breakdown point in SiOC:H low-k dielectrics

Moisture Influence on Reliability and Electrical Characteristics of SiOC:H Low-k Dielectric Material