A new approach is presented aimed at modeling mechanical stress effects which impact MOSFET electrical behavior. It is successful in accounting for mobility variations experimentally evidenced on complex MOSFET geometries. The newly developed mobility model proves to be an efficient way to include mechanical stress effects into standard simulation models. We show that stress effects can and should be taken into account in the IC design phase in present and sub 90 nm nodes CMOS generations.

Accurate Modeling of Trench Isolation Induced Mechanical Stress effects on MOSFET Electrical Performance

A method of making a semiconductor device includes patterning a fin in a substrate; forming a gate between source/drain regions over the substrate, the gate having a dielectric spacer along a sidewall; removing a portion of the dielectric spacer and filling with a metal oxide to form a spacer having a first spacer portion and a second spacer portion; forming a source/drain contact over at least one of the source/drain regions; recessing the source/drain contact and forming a via contact over the source/drain contact; and forming a gate contact over the gate, the gate contact having a first gate contact portion contacting the gate and a second gate contact portion positioned over the first gate contact portion; wherein the first spacer portion isolates the first gate contact portion from the source/drain contact, and the second spacer portion isolates the second gate contact portion from the source/drain contact.

Forming a gate contact in the active area

Complementary metal-oxide semiconductor (CMOS) technology enables the integration of image sensing and image compression processing, making improvements on overall system performance possible. We present a CMOS low data rate imaging approach by implementing compressed sensing (CS). On the basis of the CS framework, the image sensor projects the image onto a separable two-dimensional (2D) basis set and measures the corresponding coefficients obtained. First, the electrical current output from the pixels in a column are combined, with weights specified by voltage, in accordance with Kirchhoff's law. The second computation is performed in an analog vector-matrix multiplier (VMM). Each element of the VMM considers the total value of each column as the input and multiplies it by a unique coefficient. Both weights and coefficients are reprogrammable through analog floating-gate (FG) transistors. The image can be recovered from a percentage of these measurements using an optimization algorithm. The percentage, which can be altered flexibly by programming on the hardware circuit, determines the image compression ratio. These novel designs facilitate image compression during the image-capture phase before storage, and have the potential to reduce power consumption. Experimental results demonstrate that the proposed method achieves a large image compression ratio and ensures imaging quality.

CMOS low data rate imaging method based on compressed sensing

A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

Gate tie-down enablement with inner spacer

Common problems with oxide-based Resistive RAM (ReRAM) are related to high variability in operating conditions and low yield. At array level, ReRAM memory cells suffer from different voltage drops seen across the cells due to the line resistances. Although research has taken steps to resolve these issues, variability combined with resistive paths remain an important characteristic for ReRAM. In this paper, the performance and reliability of ReRAM memory arrays is investigated in a 28nm FDSOI technology versus interconnects resistivity combined with device variability.

ReRAM ON/OFF resistance ratio degradation due to line resistance combined with device variability in 28nm FDSOI technology

Analog circuit designs are often biased to work in sub-threshold mode with good gate-source voltage matching performances. Depending on the process, hump effect may change the MOS characteristics for negative Bulk-Source Voltage (VBS) and have a slight impact for V BS =0V. To model the hump effect, two narrow parasitic MOS are introduced in parallel with the main device. To accurately simulate matching degradation in sub-threshold mode, these parasitic transistors, in case of hump effect, have to be considered.

Impact of hump effect on MOSFET mismatch in the sub-threshold area for low power analog applications

In this paper, analog and digital low-voltage MOSFETs having the gate contact over Shallow Trench Isolation (reference layout) or over active area (innovative layout) are studied. Using electrical parameters measurements, Linear Ramp Voltage Stress and Hot Carrier Injection stress, we demonstrate that moving the gate contact over active area does not degrade the performances and reliability of studied devices whatever the device area or oxide thickness (down to 2.1nm), and hence, could be a relevant solution in order to reduce the CMOS device area.

Study of gate contact over active area

Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress

This paper describes different solutions to decrease dynamic consumption of circuits processed on an embedded non-volatile memories CMOS 80 nm technology. Up to 25 % in dynamic power reduction is demonstrated without degrading performances and static leakages of devices and above all, with full DMR compliancy. Ring oscillator designs are used to estimate the dynamic power gain, comparing new development process (B) to reference process (A) currently in use in manufacturing.

http://ieeexplore.ieee.org/iel7/6900043/6908326/06908560.pdf

Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology

This work presents a new transistor architecture developed by reusing already existing fabrication process steps in an embedded non-volatile memory (eNVM) CMOS technology. The proposed transistor is derived from an existing high-voltage transistor and is free in terms of photomasks and process steps, making it ideal for low-cost products. The new transistor is fabricated then electrically characterized, showing good analog performances. A SPICE (Simulation Program with Integrated Circuit Emphasis) model of the new device is developed to assess its circuit-level performances through electrical circuit simulation. The in-circuit performances of the new device are evaluated based on different ring oscillator circuits. A comparison with the existing high-voltage transistor is carried out considering performance parameters such as the oscillating frequency to demonstrate the appeal of our new transistor.

Franck Julien

Papers

Impact of hump effect on MOSFET mismatch in the sub-threshold area for low power analog applications

Study of gate contact over active area

Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress

Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology

Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology