An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Methods for accurate and conformal removal of atomic layers of materials make use of the self-limiting nature of adsorption of at least one reactant on the substrate surface. In certain embodiments, a first reactant is introduced to the substrate in step (a) and is adsorbed on the substrate surface until the surface is partially or fully saturated. A second reactant is then added in step (b), reacting with the adsorbed layer of the first reactant to form an etchant. The amount of an etchant, and, consequently, the amount of etched material is limited by the amount of adsorbed first reactant. By repeating steps (a) and (b), controlled atomic-scale etching of material is achieved. These methods may be used in interconnect pre-clean applications, gate dielectric processing, manufacturing of memory devices, or any other applications where removal of one or multiple atomic layers of material is desired.

Adsorption based material removal process

A method of fabricating a semiconductor device includes preparing a semiconductor wafer having a top surface and a bottom surface. The semiconductor wafer is loaded onto a wafer chuck, and the bottom surface of the loaded semiconductor wafer faces the wafer chuck. A groove is formed in the top surface of the loaded semiconductor wafer by irradiating a second laser onto the top surface, and a reforming region is formed in the loaded semiconductor wafer under the groove by irradiating a first laser through wafer chuck and bottom surface of the semiconductor wafer into a region in which the first laser is focused. The semiconductor wafer is unloaded from the wafer chuck. The bottom surface of the semiconductor wafer is ground to decrease a thickness of the semiconductor wafer. The semiconductor wafer is separated along the groove and the reforming region, thereby forming a plurality of unit chips.

Method of Fabricating Semiconductor Device

A nanowire array is described herein. The nanowire array comprises a substrate and a plurality of nanowires extending essentially vertically from the substrate; wherein: each of the nanowires has uniform chemical along its entire length; a refractive index of the nanowires is at least two times of a refractive index of a cladding of the nanowires. This nanowire array is useful as a photodetector, a submicron color filter, a static color display or a dynamic color display.

Light absorption and filtering properties of vertically oriented semiconductor nano wires

Etching of nitride and oxide layers with reactant gases is modulated by etching in different process regimes. High etch selectivity to silicon nitride is achieved in an adsorption regime where the partial pressure of the etchant is lower than its vapor pressure. Low etch selectivity to silicon nitride is achieved in a condensation regime where the partial pressure of the etchant is higher than its vapor pressure. By controlling partial pressure of the etchant, very high etch selectivity to silicon nitride may be achieved.

Modulating etch selectivity and etch rate of silicon nitride thin films

A method and system of making a mask with a transparent substrate thereon is provided. A first resolution enhancement structure is formed on the first portion of the transparent substrate. A second resolution enhancement structure is formed on a second portion of the transparent substrate, with the second resolution enhancement structure different from the first resolution enhancement structure.

Semiconductor manufacturing resolution enhancement system and method for simultaneously patterning different feature types

A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. The hard mask is of a material formulated for removal without damaging the charge-trapping dielectric layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A salicide is grown without short-circuiting the first and second bitlines.

Hard mask process for memory device without bitline shorts

The invention is a semiconductor device and a method of forming the semiconductor device. The semiconductor device comprises a substrate; buried bitlines formed in the substrate narrower than achievable at a resolution limit of lithography; a doped region formed adjacent at least one of the buried bitlines; a charge trapping layer disposed over the substrate; and a conductive layer disposed over the charge trapping layer, wherein the doped region adjacent the least one of the buried bitlines inhibits a leakage current between the buried bitlines.

Bitline hard mask spacer flow for memory cell scaling

A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric material. First and second bitlines are implanted and a wordline material is deposited. A hard mask material is deposited over the wordline material. The hard mask material is of a material having the characteristic of being deposited rather than grown. A photoresist material is deposited over the wordline material and is patterned to form a patterned hard mask. The patterned photoresist material is removed. The wordline material is processed using the patterned hard mask to form a wordline. The patterned hard mask material is removed.

Memory wordline hard mask

A device and method for manufacturing thereof for a MirrorBit® Flash memory includes providing a semiconductor substrate and successively depositing a first insulating layer, a charge-trapping layer, and a second insulating layer. First and second bitlines are implanted and wordlines are formed before completing the memory. Spacers are formed between the wordlines and an inter-layer dielectric layer is formed over the wordlines. One or more of the second insulating layer, wordlines, spacers, and inter-layer dielectric layers are deuterated, replacing hydrogen bonds with deuterium, thus improving data retention and substantially reducing charge loss.

Jean Y. Yang

Papers

Semiconductor manufacturing resolution enhancement system and method for simultaneously patterning different feature types

Hard mask process for memory device without bitline shorts

Bitline hard mask spacer flow for memory cell scaling

Memory wordline hard mask

Semiconductor memory with deuterated materials