http://ieeexplore.ieee.org/iel5/5610941/5624686/05624745.pdf

Power electronics

Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.

/pdf/3-d-ics-a-novel-chip-design-for-improving-deep-submicrometer-6k9by1rs19.pdf

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

A review on electrochemical double-layer capacitors

Supercapacitors (SCs) have high power density and exceptional durability. Progress has been made in their materials and chemistries, while extensive research has been carried out to address challenges of SC management. The potential engineering applications of SCs are being continually explored. This paper presents a review of SC modeling, state estimation, and industrial applications reported in the literature, with the overarching goal to summarize recent research progress and stimulate innovative thoughts for SC control/management. For SC modeling, the state-of-the-art models for electrical, self-discharge, and thermal behaviors are systematically reviewed, where electrochemical, equivalent circuit, intelligent, and fractional-order models for electrical behavior simulation are highlighted. For SC state estimation, methods for State-of-Charge (SOC) estimation and State-of-Health (SOH) monitoring are covered, together with an underlying analysis of aging mechanism and its influencing factors. Finally, a wide range of potential SC applications is summarized. Particularly, co-working with high energy-density devices constitutes hybrid energy storage for renewable energy systems and electric vehicles (EVs), sufficiently reaping synergistic benefits of multiple energy-storage units.

A review of supercapacitor modeling, estimation, and applications: A control/management perspective

http://www.te.kmutnb.ac.th/~ptt/publications/J11_2009_5.pdf

Energy management of fuel cell/battery/supercapacitor hybrid power source for vehicle applications

Although many researchers have investigated the use of different powertrain topologies, component sizes, and control strategies in fuel-cell vehicles, a detailed parametric study of the vehicle types must be conducted before a fair comparison of fuel-cell vehicle types can be performed. This paper compares the near-optimal configurations for three topologies of vehicles: fuel-cell-battery, fuel-cell-ultracapacitor, and fuel-cell-battery-ultracapacitor. The objective function includes performance, fuel economy, and powertrain cost. The vehicle models, including detailed dc/dc converter models, are programmed in Matlab/Simulink for the customized parametric study. A controller variable for each vehicle type is varied in the optimization.

A Comparative Study of Fuel-Cell–Battery, Fuel-Cell–Ultracapacitor, and Fuel-Cell–Battery–Ultracapacitor Vehicles

Two of the main challenges for electric vehicle (EV) adoption include limited range and long recharge times. Ultrafast charging can help to mitigate both these concerns. However, for typical 400-V battery EVs (BEVs), the charging rate is limited by the practical cable size required to carry the charging current. To reach ultrahigh charge rates of 350 or 400 kW, 800-V BEVs are a promising alternative. However, the design of an 800-V EV requires careful new considerations for all electrical systems. This article reviews the current state of 800-V vehicle powertrain electrical design and performs an analysis of benefits, challenges, and future trends regarding multiple vehicle powertrain components. Specifically, detailed benefits and challenges related to the battery, propulsion motor, inverter, auxiliary power unit, and on- and off-board chargers are discussed.

800-V Electric Vehicle Powertrains: Review and Analysis of Benefits, Challenges, and Future Trends

Electric vehicle (EV) adoption continues to rise, yet EV sales still represent a small portion of vehicle sales in most countries. An expansion of the dc fast-charging (DCFC) network is likely to accelerate this revolution toward sustainable transportation, giving drivers more flexible options for charging on longer trips. However, DCFC presents a large load on the grid, which can lead to costly grid reinforcements and high monthly operating costs—adding energy storage to the DCFC station can help mitigate these challenges. This article performs a comprehensive review of DCFC stations with energy storage, including motivation, architectures, power electronic converters, and detailed simulation analysis for various charging scenarios. The review is closely tied to current state-of-the-art technologies and covers both academic research contributions and real energy storage projects in operation around the world.

A Comprehensive Review of DC Fast-Charging Stations With Energy Storage: Architectures, Power Converters, and Analysis

UltraSPARC is the first microprocessor from Sun Microsystems' SPARC Technology Business to implement the new 64-bit SPARC V9 architecture. ULtraSPARC is equipped with unique multimedia capabilities and is capable of 4-way superscalar instruction dispatch, with an emphasis on maximal system efficiency and throughput in the execution of complex, memory-intensive applications. UltraSPARC maintains a strict binary compatibility with the thousands of existing 32-bit applications developed for other SPARC processors. This paper describes the feature set and operation of UItraSPARC.

UltraSPARC: the next generation superscalar 64-bit SPARC

A transimpedance amplifier packaged with an InP p-i-n photodiode has been demonstrated for 10-Gb/s SONET receiver. The shunt feedback transimpedance amplifier is fabricated in 0.25-/spl mu/m modular Si BiCMOS technology. The transimpedance of 55 dB/spl Omega/ is achieved at a bandwidth of 9 GHz by applying shunt peaking and filter termination at the input. The optical sensitivity of -17 dBm was measured at 10 Gb/s for a bit-error rate of 10/sup -12/.

Jennifer Bauman

Papers

A Comparative Study of Fuel-Cell–Battery, Fuel-Cell–Ultracapacitor, and Fuel-Cell–Battery–Ultracapacitor Vehicles

800-V Electric Vehicle Powertrains: Review and Analysis of Benefits, Challenges, and Future Trends

A Comprehensive Review of DC Fast-Charging Stations With Energy Storage: Architectures, Power Converters, and Analysis

UltraSPARC: the next generation superscalar 64-bit SPARC

A Si BiCMOS transimpedance amplifier for 10-Gb/s SONET receiver