An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Power semiconductor devices and methods of manufacture

This invention generally relates to power semiconductor devices, and in particular to improved thyristor devices and circuits. The techniques we describe are particularly useful for so-called MOS-gated thyristors. We describe a thyristor comprising a plurality of power thyristor devices connected in parallel, each said thyristor device being operable at a device current which the device has an on-resistance with a positive temperature coefficient.

Power Semiconductor Devices

Semiconductor Power Devices

AlGaN-GaN power high-electron mobility transistors (HEMTs) with 600-V breakdown voltage are fabricated and demonstrated as switching power devices for motor drive and power supply applications. The fabricated power HEMT realized the high breakdown voltage by optimized field plate technique and the low on-state resistance of 3.3 m/spl Omega/cm/sup 2/, which is 20 times lower than that or silicon MOSFETs, thanks to the high critical field of GaN material and the high mobility in 2DEG channel. The fabricated devices also demonstrated the high current density switching of 850 A/cm/sup 2/ turn-off. These results show that AlGaN-GaN power-HEMTs are one of the most promising candidates for future switching power device for power electronics applications.

High breakdown voltage AlGaN-GaN power-HEMT design and high current density switching behavior

Production of a channel zone (12a, 12b) in a transistor comprises structuring a polysilicon layer (11) via the channel zone to be formed and using as a mask substrate for the following doping of the channel zone An Independent claim is also included for a PMOS field effect transistor cell having a channel zone lying below a polysilicon layer

Production of a channel zone in a transistor e.g. vertical depletion-MOSFET transistor cell, comprises structuring a polysilicon layer via the channel zone to be formed

Teilnehmerleitungen werden gegen durch Blitzeinwirkung oder induktiv von Hochspannungsleitungen erzeugte Uberspannungen durch einen feldgesteuerten Thyristor (1) geschutzt, der zwischen einer Ader der Teilnehmerleitung und Masse liegt. Der Thyristor wird uber eine integrierte Zenerdiodenkette (3) gezundet. Die Zenerdiodenkette weist Kurzschlusbrucken (4) auf, die nach Masgabe einer vorgegebenen Durchbruchsspannung unterbrochen werden. Damit ist die Schutzspannung auf einfache Weise unabhangig von den Eigenschaften des fur den Thyristor (1) verwendeten Halbleitermaterials einstellbar.

Integrated-circuit arrangement for the protection of subscriber lines against overvoltages

The invention relates to a junction-gate field-effect transistor comprising a semiconductor zone (10) which presents an inner area (13) as well as a first (22) and a second (32) connecting area. The first connecting area (22) is of the same conductivity type as the inner area (13) but has a higher doping concentration and the second connecting area (32) is of a conductivity type opposite to that of the inner area (13). This reduces forward resistance while maintaining a high blocking voltage strength.

Jenö Dr. Tihanyi

Papers

Production of a channel zone in a transistor e.g. vertical depletion-MOSFET transistor cell, comprises structuring a polysilicon layer via the channel zone to be formed

Integrated-circuit arrangement for the protection of subscriber lines against overvoltages

Junction-gate field-effect transistor with highly doped connecting areas