IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

With the relentless scaling of semiconductor technology, the lifetime reliability of embedded multiprocessor platforms has become one of the major concerns for the industry. If this is not taken into consideration during the task allocation and scheduling process, some processors might age much faster than the others and become the reliability bottleneck for the system, thus significantly reducing the system's service life. To tackle this problem, in this paper, we propose an analytical model to estimate the lifetime reliability of multiprocessor platforms when executing periodical tasks, and we present a novel lifetime reliability-aware task allocation and scheduling algorithm based on simulated annealing technique. In addition, to speed up the annealing process, several techniques are proposed to simplify the design space exploration process with satisfactory solution quality. Experimental results on various multiprocessor platforms and task graphs demonstrate the efficacy of the proposed approach.

Lifetime reliability-aware task allocation and scheduling for MPSoC platforms

Microarchitectural redundancy has been proposed as a means of improving chip lifetime reliability. It is typically used in a reactive way, allowing chips to maintain operability in the presence of failures by detecting and isolating, correcting, and/or replacing components on a first-come, first-served basis only after they become faulty. In this paper, we explore an alternative, more preferred method of exploiting microarchitectural redundancy to enhance chip lifetime reliability. In our proposed approach, redundancy is used proactively to allow non-faulty microarchitecture components to be temporarily deactivated, on a rotating basis, to suspend and/or recover from certain wearout effects. This approach improves chip lifetime reliability by warding off the onset of wearout failures as opposed to reacting to them posteriorly. Applied to on-chip cache SRAM for combating NBTI-induced wearout failure, our proactive wearout recovery approach increases lifetime reliability (measured in mean-time-to-failure) of the cache by about a factor of seven relative to no use of microarchitectural redundancy and a factor of five relative to conventional reactive use of redundancy having similar area overhead.

A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime

Nanoscale technology nodes bring reliability concerns back to the center stage of digital system design. A systematic classification of approaches that increase system resilience in the presence of functional hardware (HW)-induced errors is presented, dealing with higher system abstractions, such as the (micro)architecture, the mapping, and platform software (SW). The field is surveyed in a systematic way based on nonoverlapping categories, which add insight into the ongoing work by exposing similarities and differences. HW and SW solutions are discussed in a similar fashion so that interrelationships become apparent. The presented categories are illustrated by representative literature examples to illustrate their properties. Moreover, it is demonstrated how hybrid schemes can be decomposed into their primitive components.

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Classification of Resilience Techniques Against Functional Errors at Higher Abstraction Layers of Digital Systems

This article reviews the existing work in self-healing and self-repairing technologies, including work in software engineering, materials, mechanics, electronics, MEMS, self-reconfigurable robotics, and others. It suggests a terminology and taxonomy for self-healing and self-repair, and discusses the various related types of other self-* properties. The mechanisms and methods leading to self-healing are reviewed, and common elements across disciplines are identified.

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Self-healing and self-repairing technologies

This paper tackles the issue of modeling chip lifetime reliability at the architecture level. We propose a new and robust structure-aware lifetime reliability model at the architecture-level, where devices only vulnerable to failure mechanisms and the effective stress condition of these devices are taken into account for the failure rate of microarchitecture structures. In addition, we present this reliability analysis framework based on a new concept, called the FIT of reference circuit or FORC, which allows architects to quantify failure rates without having to delve into low-level circuit- and technology-specific details of the implemented architecture. This is done through a onetime characterization of a reference circuit needed to quantify the reference FITs for each class of modeled failure mechanisms for a given technology and implementation style. With this new reliability modeling framework, architects are empowered to proceed with architecture-level reliability analysis independent of technological and environmental parameters.

A Framework for Architecture-Level Lifetime Reliability Modeling

This paper provides: 1) a very brief motivation and technological trend data to show why hard and soft errors are expected to be of increasing concern in the future; 2) a summary review of chip-level error tolerance practices today-with a brief reference to IBM's POWER6 and POWER7 designs; 3) open research challenges and current solution approaches of promise, based on published literature; and 4) concluding remarks.

Error Tolerance in Server Class Processors

Modern processor systems are equipped with on-chip or on-board power controllers. In this paper, we examine the challenges and pitfalls in architecting such dynamic power management control systems. A key question that we pose is: How to ensure that such managed systems are "energy-secure" and how to pursue pre-silicon modeling to ensure such security? In other words, we address the robustness and security issues of such systems. We discuss new advances in energy-secure power management, starting with an assessment of potential vulnerabilities in systems that do not address such issues up front.

Power management of multi-core chips: challenges and pitfalls

A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.

Adaptive workload based optimizations to mitigate current delivery limitations in integrated circuits

A method for extending lifetime reliability of CMOS circuitry includes configuring a logic high supply rail, a logic low supply rail, and a virtual supply rail. In an intense recovery mode of operation, a first switching device is rendered nonconductive to isolate the virtual supply rail from the one of the logic high supply rail and the logic low supply rail, and the second switching device is rendered conductive so as to equalize the voltage on the virtual supply rail and the other of the logic high supply rail and the logic low supply rail. At least one device within the circuitry provides one of the logic high voltage and the logic low voltage to a gate terminal of an FET within the circuitry, with a source terminal of the FET coupled to the virtual supply rail, such that the FET is subjected to a reverse bias condition.

Jeonghee Shin

Papers

A Framework for Architecture-Level Lifetime Reliability Modeling

Error Tolerance in Server Class Processors

Power management of multi-core chips: challenges and pitfalls

Adaptive workload based optimizations to mitigate current delivery limitations in integrated circuits

Method for extending lifetime reliability of digital logic devices through reversal of aging mechanisms