P
Pradip Bose
Researcher at IBM
Publications - 269
Citations - 9344
Pradip Bose is an academic researcher from IBM. The author has contributed to research in topics: Power management & Microarchitecture. The author has an hindex of 49, co-authored 264 publications receiving 8910 citations.
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Proceedings ArticleDOI
An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget
TL;DR: The results show that the best architected policies can come within 1% of the performance of an ideal oracle, while meeting a given chip-level power budget, and are significantly better than static management, even if static scheduling is given oracular knowledge.
Proceedings ArticleDOI
The impact of technology scaling on lifetime reliability
TL;DR: The results imply that leveraging a single microarchitecture design for multiple remaps across a few technology generations will become increasingly difficult, and motivate a need for workload specific, microarch Architectural lifetime reliability awareness at an early design stage.
Journal ArticleDOI
Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors
David Brooks,Pradip Bose,Stanley Everett Schuster,Hans M. Jacobson,Prabhakar Kudva,Alper Buyuktosunoglu,John-David Wellman,Victor Zyuban,Meeta S. Gupta,Peter William Cook +9 more
TL;DR: The approach of using energy-enabled performance simulators in early design, examining some of the emerging paradigms in processor design and comment on their inherent power-performance characteristics, is described.
Journal ArticleDOI
The Case for Lifetime Reliability-Aware Microprocessors
TL;DR: This paper proposes dynamic reliability management (DRM) - a technique where the processor can respond to changing application behavior to maintain its lifetime reliability target, and describes an architecture-level model and its implementation that can dynamically track lifetime reliability, responding to changes in application behavior.
Proceedings ArticleDOI
Microarchitectural techniques for power gating of execution units
TL;DR: In this article, the potential of architectural techniques to reduce leakage through power-gating of execution units was explored, for the range of relevant break-even points determined by the analytical equations, using a state-of-the-art out-oforder superscalar processor model.