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Alper Buyuktosunoglu
Researcher at IBM
Publications - 195
Citations - 5700
Alper Buyuktosunoglu is an academic researcher from IBM. The author has contributed to research in topics: Power management & Cache. The author has an hindex of 34, co-authored 187 publications receiving 5358 citations. Previous affiliations of Alper Buyuktosunoglu include University of Rochester.
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Proceedings ArticleDOI
An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget
TL;DR: The results show that the best architected policies can come within 1% of the performance of an ideal oracle, while meeting a given chip-level power budget, and are significantly better than static management, even if static scheduling is given oracular knowledge.
Journal ArticleDOI
Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors
David Brooks,Pradip Bose,Stanley Everett Schuster,Hans M. Jacobson,Prabhakar Kudva,Alper Buyuktosunoglu,John-David Wellman,Victor Zyuban,Meeta S. Gupta,Peter William Cook +9 more
TL;DR: The approach of using energy-enabled performance simulators in early design, examining some of the emerging paradigms in processor design and comment on their inherent power-performance characteristics, is described.
Proceedings ArticleDOI
Microarchitectural techniques for power gating of execution units
TL;DR: In this article, the potential of architectural techniques to reduce leakage through power-gating of execution units was explored, for the range of relevant break-even points determined by the analytical equations, using a state-of-the-art out-oforder superscalar processor model.
Proceedings ArticleDOI
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
TL;DR: This paper proposes a cache and TLB layout and design that leverages repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis and demonstrates that a configurable L2/L3 cache hierarchy coupled with a conventional LI results in an average 43% reduction in memory hierarchy energy in addition to improved performance.
Proceedings ArticleDOI
NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads
Seth H. Pugsley,Jeffrey Jestes,Huihui Zhang,Rajeev Balasubramonian,Vijayalakshmi Srinivasan,Alper Buyuktosunoglu,Al Davis,Feifei Li +7 more
TL;DR: A number of key elements necessary in realizing efficient NDC operation are described and evaluated, including low-EPI cores, long daisy chains of memory devices, and the dynamic activation of cores and SerDes links.