Journal ArticleDOI
Embedded deterministic test
TLDR
This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time.Abstract:
This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The presented scheme is widely applicable and easy to deploy because it is based on the standard scan/ATPG methodology and adopts a very simple flow. It is nonintrusive as it does not require any modifications to the core logic such as the insertion of test points or logic bounding unknown states. The EDT scheme consists of logic embedded on a chip and a new deterministic test-pattern generation technique. The main contributions of the paper are test-stimuli compression schemes that allow us to deliver test data to the on-chip continuous-flow decompressor. In particular, it can be done by repeating certain patterns at the rates, which are adjusted to the requirements of the test cubes. Experimental results show that for industrial circuits with test cubes with very low fill rates, ranging from 3% to 0.2%, these schemes result in compression ratios of 30 to 500 times. A comprehensive analysis of the encoding efficiency of the proposed compression schemes is also provided.read more
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Book
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
TL;DR: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time- to-volume.
Journal ArticleDOI
Survey of Test Vector Compression Techniques
TL;DR: This article summarizes and categories hardware-based test vector compression techniques for scan architectures, which fall broadly into three categories: code-based schemes use data compression codes to encode test cubes; linear-decompression- based schemes decompress the data using only linear operations; and broadcast-scan-based scheme rely on broadcasting the same values to multiple scan chains.
Book
VLSI Test Principles and Architectures: Design for Testability
TL;DR: A comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time to market and time-to-volume as mentioned in this paper.
Proceedings ArticleDOI
Testing 3D chips containing through-silicon vias
TL;DR: This Embedded Tutorial provides an overview of the manufacturing steps of TSV-based 3D chips and their associated test challenges, and discusses the necessary flows for wafer-level and package-level tests, the challenges with respect to test contents and wader-level probe access, and the on-chip DfT infrastructure required for 3D-SICs.
References
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Journal ArticleDOI
Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers
TL;DR: A new scheme for built-in test that uses multiple-polynomial linear feedback shift registers (MP-LFSR's) and an implicit polynomial identification reduces the number of extra bits per seed to one bit is presented.
Proceedings ArticleDOI
Embedded deterministic test for low cost manufacturing test
Janusz Rajski,Jerzy Tyszer,M. Kassab,Nilanjan Mukherjee,Rob Thompson,Kun-Han Tsai,A. Hertwig,Nagesh Tamarapalli,Grzegorz Mrugalski,Geir Eide,Jun Qian +10 more
TL;DR: Embedded deterministic test technology is introduced, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time.