Spiking neural networks (SNNs) attempt to emulate information processing in the mammalian brain based on massively parallel arrays of neurons that communicate via spike events. SNNs offer the possibility to implement embedded neuromorphic circuits, with high parallelism and low power consumption compared to the traditional von Neumann computer paradigms. Nevertheless, the lack of modularity and poor connectivity shown by traditional neuron interconnect implementations based on shared bus topologies is prohibiting scalable hardware implementations of SNNs. This paper presents a novel hierarchical network-on-chip (H-NoC) architecture for SNN hardware, which aims to address the scalability issue by creating a modular array of clusters of neurons using a hierarchical structure of low and high-level routers. The proposed H-NoC architecture incorporates a spike traffic compression technique to exploit SNN traffic patterns and locality between neurons, thus reducing traffic overhead and improving throughput on the network. In addition, adaptive routing capabilities between clusters balance local and global traffic loads to sustain throughput under bursting activity. Analytical results show the scalability of the proposed H-NoC approach under different scenarios, while simulation and synthesis analysis using 65-nm CMOS technology demonstrate high-throughput, low-cost area, and power consumption per cluster, respectively.

Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations

Routing algorithms for NoCs were extensively studied in the last 12 years, and proposals for algorithms targeting some cost function, as latency reduction or congestion avoidance, abound in the literature. Fault-tolerant routing algorithms were also proposed, being the table-based approach the most adopted method. Considering SoCs with hundred of cores in a near future, features as scalability, reachability, and fault assumptions should be considered in the fault-tolerant routing methods. However, the current proposals some have some limitations: (1) increasing cost related to the NoC size, compromising scalability; (2) some healthy routers may not be reached even if there is a source-target path; (3) some algorithms restricts the number of faults and their location to operate correctly. The present work presents a method, inspired in VLSI routing algorithms, to search the path between source-target pairs where the network topology is abstracted. Results present the routing path for different topologies (mesh, torus, Spidergon and Hierarchical-Spidergon) in the presence of faulty routers. The silicon area overhead and total execution time of the path computation is small, demonstrating that the proposed method may be adopted in NoC designs.

Topology-agnostic fault-tolerant NoC routing method

Due to the shrinking transistor sizes, the density of ICs roughly doubles every year as predicted by Moore's law. These advancements in the VLSI integration densities towards the nano scale era, witnessed a paradigm shift from computation centric designs to communication centric designs incorporating very large number of simple cores. Plenty of traditional interconnect schemes like point to point, buses and crossbars are available to interconnect small number of cores. While achieving fast and efficient communication with point to point communication schemes, wire density is a barrier for adapting them to many core architectures. Moreover, buses are simpler in design, they suffer from the scalability and arbitration issues along with bandwidth bottleneck as the number of cores increases. Similarly area and power requirements of a crossbar limits its applicability. Hence, in many core architectures like Chip Multiprocessors (CMP) and Multi processor System-on-Chip (MPSoCs), emerge the need of an efficient communication infrastructure as traditional solutions fails to handle the communication challenges. Network-on-Chip (NoC), a scalable and modular design approach, has been proposed as a promising alternative to traditional bus based architectures for inter-core communication. NoC has also been accepted in industy (Tilera's TILE-Gx72, TILE64TM [1] processors and Intel's terascale processor [2]. NoCs are an attractive alternative for the traditional shared-buses or dedicated wires due to many reasons. First, NoCs represent a scalable solution to on-chip communication paradigm, because they provide scalable bandwidth at low power and area overheads. Second, NoCs are very efficient in terms of use of wiring and multiplexing many traffic flows on the same channels providing quality of service and higher bandwidth. Finally, on-chip networks with regular topologies have short interconnects that can be optimized and reused using regular iterative blocks, thus making the verification process easy. For on-chip networks, two-dimensional (2D) mesh is the most preferred topology choice due to its regularity, scalability, and perfect physical layout on an actual chip. This tutorial shall focus on NoC routing algorithms, their implementations and issues. The main parameters of the network which are affected by the routing algorithm include fault-tolerance, quality of service, communication performance (throughput and latency) and power consumption. The following are the main objective of this tutorial: • Introduction to NoC [3]: In this part, we briefly discuss about various design parameters of NoC such as topology, switching, flow control, routing and comparison with existing mechanisms. • Routing Taxonomy [4]: In this part, we present classification of various routing algorithms. • Deadlock and Livelock freedom in Routing: One of current issue in NoC routing is the use of acyclic channel dependency graph (ACDG) for deadlock freedom prohibiting certain routing turns. Thus, ACDG reduces the degree of adaptiveness. In this section, we discuss various turn models [5] and how these turn model can be improved to increase adaptivity while maintaining deadlock freedom. • Routing Implementations for NoC: Denser integration advancements make the chip more prone to failures (deep sub-micron effects, manufacturing effects etc). Furthermore these failures may disrupt the regularity of 2D meshes, leading to an irregular set of topologies generated from regular 2D meshes. Under this condition, solutions of regular 2D meshes may no longer work due to irregular topology. In this section, we discuss state-of-art routing implementation techniques [6]-[8] used for irregular 2D mesh under different failures. • Learning methods to handle congestion in Routing: Reinforcement Learning (RL) is a machine learning paradigm that has been widely applied in many areas. The Q-Learning has been used in NOC to learn the network traffic and make the routing decisions accordingly. At each node, a table is used to store the values that represent the congestion level of each link and these values are updated after every packet transfer. Although, Q-Learning has improved network performance but there are many challenges which we would discuss in this section • Brief hands on tool chain for NoC simulation shall also provide towards the end.

Network-on-chip: Current issues and challenges

This paper introduces a new, practical routing algorithm, Maze-routing, to tolerate faults in network-on-chips. The algorithm is the first to provide all of the following properties at the same time: 1) fully-distributed with no centralized component, 2) guaranteed delivery (it guarantees to deliver packets when a path exists between nodes, or otherwise indicate that destination is unreachable, while being deadlock and livelock free), 3) low area cost, 4) low reconfiguration overhead upon a fault. To achieve all these properties, we propose Maze-routing, a new variant of face routing in on-chip networks and make use of deflections in routing. Our evaluations show that Maze-routing has 16X less area overhead than other algorithms that provide guaranteed delivery. Our Maze-routing algorithm is also high performance: for example, when up to 5 links are broken, it provides 50% higher saturation throughput compared to the state-of-the-art.

/pdf/a-low-overhead-fully-distributed-guaranteed-delivery-routing-26777a9i88.pdf

A Low-Overhead, Fully-Distributed, Guaranteed-Delivery Routing Algorithm for Faulty Network-on-Chips

With the advent of deep sub-micron technology, fault-tolerant solutions are needed to keep many-core chips operative. In NoCs, Logic Based Distributed Routing (LBDR) proved to be a flexible routing framework for 2D meshes with link and router faults. However, to provide full coverage, LBDR requires a module named FORKS which replicates some messages. This imposes the use of virtual cut-through switching and a complex router arbiter, increasing excessively the router cost, mainly in buffer area. Also, some failure combinations require the use of a non-trivial dynamic reconfiguration strategy to avoid deadlocks. We propose d2-LBDR which adds, on every router, a distance register to the closest failure. This enables the support of more failure combinations without an excessive implementation cost. Indeed, we restore the use of wormhole switching, keeping router architecture simple, while achieving the same fault coverage as the best LBDR version, without requiring complex switching strategies nor any dynamic reconfiguration strategy. Results show that a small area overhead (3%) is enough for the implementation of a fully flexible routing method without any limiting support case when compared with LBDR. d2-LBDR reduces area overhead over the best LBDR approach (300% overhead against 3%) while preserving fault coverage. Results show d2-LBDR performance equal to LBDR.

d 2 -LBDR: Distance-driven routing to handle permanent failures in 2D mesh NoCs

The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area, and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism, or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge. This paper presents universal logic-based distributed routing (uLBDR), an efficient logic-based mechanism that adapts to any irregular topology derived from 2-D meshes, instead of using routing tables. uLBDR requires a small set of configuration bits, thus being more practical than large routing tables implemented in memories. Several implementations of uLBDR are presented highlighting the tradeoff between routing cost and coverage. The alternatives span from the previously proposed LBDR approach (with 30% of coverage) to the uLBDR mechanism achieving full coverage. This comes with a small performance cost, thus exhibiting the tradeoff between fault tolerance and performance. Power consumption, area, and delay estimates are also provided highlighting the efficiency of the mechanism. To do this, different router models (one for CMPs and one for MPSoCs) have been designed as a proof concept.

/pdf/cost-efficient-on-chip-routing-implementations-for-cmp-and-b45mqtm7ey.pdf

Jesús Camacho

Papers

Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems