In very-large multiple-input multiple-output (MIMO) systems, the base station (BS) is equipped with very large number of antennas as compared to previously considered systems. There are various advantages of increasing the number of antennas, and some schemes require handling large matrices for joint processing (pre-coding) at the BS. The dirty paper coding (DPC) is an optimal pre-coding scheme and has a very high complexity. However, with increasing number of BS antennas, linear pre-coding performance tends to that of the optimal DPC. Although linear pre-coding is less complex than DPC, there is a need to compute pseudo inverses of large matrices. In this paper we present a low complexity approximation of down-link Zero Forcing (ZF) linear pre-coding for very-large multi-user MIMO systems. Approximation using a Neumann series expansion is opted for inversion of matrices over traditional exact computations, by making use of special properties of the matrices, thereby reducing the cost of hardware. With this approximation of linear pre-coding, we can significantly reduce the computational complexity for large enough systems, i.e., where we have enough BS antenna elements. For the investigated case of 8 users, we obtain 90% of the full ZF sum rate, with lower computational complexity, when the number of BS antennas per user is about 20 or more.

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Approximative matrix inverse computations for very-large MIMO and applications to linear pre-coding systems

In very-large multiple-input multiple-output (MIMO) systems, the BS (base station) is equipped with very large number of antennas as compared to previously considered systems. There are various advantages of increasing the number of antennas, and some schemes would require handling large matrices for joint processing (pre-coding) at the base station. The dirty paper coding (DPC) is an optimal pre-coding scheme and has a very high complexity. However with increasing number of BS antennas linear pre-coding performance tends to that of the optimal DPC. Although linear pre-coding is less complex than DPC, there is a need to compute pseudo inverses of large matrices. In this paper we present a low complexity approximation of down-link Zero Forcing linear pre-coding for very-large multi-user MIMO systems. Approximation using a Neumann series expansion is opted for inversion of matrices over traditional exact computations, by making use of special properties of the matrices, thereby reducing the cost of hardware. With this approximation of linear pre-coding, we can significantly reduce the computational complexity for large enough systems, i.e., where we have enough BS antenna elements. For the investigated case of 8 users, we obtain 90% of the full ZF sum rate, with lower computational complexity, when the number of BS antennas per user is about 20 or more. (Less)

/pdf/approximative-matrix-inverse-computations-for-very-large-11jc7svqyb.pdf

Approximative Matrix Inverse Computations for Very-large MIMO and Applications to Linear Pre-coding Systems

Practical data detectors for future wireless systems with hundreds of antennas at the base station must achieve high throughput and low error rate at low complexity. Since the complexity of maximum-likelihood (ML) data detection is prohibitive for such large wireless systems, approximate methods are necessary. In this paper, we propose a novel data detection algorithm referred to as Triangular Approximate SEmidefinite Relaxation (TASER), which is suitable for two application scenarios: i) coherent data detection in large multi-user multiple-input multiple-output (MU-MIMO) wireless systems and ii) joint channel estimation and data detection in large single-input multiple-output (SIMO) wireless systems. For both scenarios, we show that TASER achieves near-ML error-rate performance at low complexity by relaxing the associated ML-detection problems into a semidefinite program, which we solve approximately using a preconditioned forward-backward splitting procedure. Since the resulting problem is non-convex, we provide convergence guarantees for our algorithm. To demonstrate the efficacy of TASER in practice, we design a systolic architecture that enables our algorithm to achieve high throughput at low hardware complexity, and we develop reference field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) designs for various antenna configurations.

Data Detection in Large Multi-Antenna Wireless Systems via Approximate Semidefinite Relaxation

This paper develops a new distributed power control scheme for a power-splitting-based interference channel (IFC) with simultaneous wireless information and power transfer (SWIPT). The considered IFC consists of multiple source-destination pairs. Each destination splits its received signal into two parts for information decoding (ID) and energy harvesting (EH), respectively. Each pair adjusts its transmit power and power splitting ratio to meet both the signal-to-interference-plus-noise ratio (SINR) and EH constraints at its corresponding destination. To characterize rational behaviors of source-destination pairs, we formulate a noncooperative game for the considered system, where each pair is modeled as a strategic player who aims to minimize its own transmit power under both SINR and EH constraints at the destination. We derive a sufficient and necessary condition for the existence and uniqueness of the Nash equilibrium (NE) of the formulated game. The best response strategy of each player is derived, and then the NE can be achieved iteratively. Numerical results show that the proposed game-theoretic approach can achieve a near-optimal performance under various SINR and EH constraints.

Distributed Power Control in Interference Channels With QoS Constraints and RF Energy Harvesting: A Game-Theoretic Approach

As a branch of sphere decoding, the K -best method has played an important role in detection in large-scale multiple-input-multiple-output (MIMO) systems. However, as the numbers of users and antennas grow, the preprocessing complexity increases significantly, which is one of the major issues with the K -best method. To address this problem, this paper proposes a preprocessing algorithm combining Cholesky sorted QR decomposition and partial iterative lattice reduction (CHOSLAR) for K -best detection in a 64-quadrature amplitude modulation (QAM) 16 $\times$ 16 MIMO system. First, Cholesky decomposition is conducted to perform sorted QR decomposition. Compared with conventional sorted QR decomposition, this method reduces the number of multiplications by 25.1% and increases parallelism. Then, a constant-throughput partial iterative lattice reduction method is adopted to achieve near-optimal detection accuracy. This method further increases parallelism, reduces the number of matrix swaps by 45.5%, and reduces the number of multiplications by 67.3%. Finally, a sorting-reduced K -best strategy is used for vector estimation, thereby, reducing the number of comparators by 84.7%. This method suffers an accuracy loss of only approximately 1.44 dB compared with maximum likelihood detection. Based on CHOSLAR, this paper proposes a fully pipelined very-large-scale-integration architecture. A series of different systolic arrays and parallel processing units achieves an optimal tradeoff among throughput, area consumption, and power consumption. This architectural layout is obtained via TSMC 65-nm 1P9M CMOS technology, and throughput metrics of 1.40 Gbps/W (throughput/power) and 0.62 Mbps/kG (throughput/area) are achieved, demonstrating that the proposed system is much more efficient than state-of-the-art designs.

Algorithm and Architecture of a Low-Complexity and High-Parallelism Preprocessing-Based K -Best Detector for Large-Scale MIMO Systems

This paper presents the VLSI implementation of a lattice-reduction-aided (LRA) detection system. The proposed system includes a QR decomposition, lattice reduction (LR) processor, and sorting-reduced (SR) K-best detector for 8 $\,\times\,$ 8 multiple-input multiple-output (MIMO) systems. The bit error rate of the proposed MIMO detection system only incurs approximately 3 dB of implementation loss compared with optimal maximum likelihood detection with 64-quadratic-amplitude modulation. The proposed processor can also support different throughput requirements by adjusting the stage number of LR. The SR K-best detector can achieve 3.1 Gb/s throughput with 0.24-ns latency. The throughput of the system reaches 585 Mb/s if one channel preprocessing can support 72 symbol detections. The corresponding energy per bit is 63 pJ/bit, which is the smallest value achieved to date. This paper presents the first VLSI implementation of a complete LRA K-best detector with an 8 $\,\times\,$ 8 dimension.

A 3.1 Gb/s 8 $\,\times\,$ 8 Sorting Reduced K-Best Detector With Lattice Reduction and QR Decomposition

Due to the growing demand of transmission capacity of the wireless communication system, multiple-input multiple-output orthogonal-frequency-division-multiplexing (MIMO-OFDM) communication system requires more and more MIMO antennas and a large number of OFDM subcarriers. Thus, the QR decomposition becomes one of the computational bottlenecks in the QR-based MIMO detection. The proposed Givens-Rotation-based QR decomposition algorithm features efficient parallel processing with sorting function that resolves the trade-off between the detection performance and hardware utiliztion efficiency. According to the algorithm, we designed and implemented a 2×2∼8×8 QR decomposition processor using TSMC 0.18/μm 1P6M CMOS technology. The throughput of the QR decomposition processor achieves 6.8×104 SQRD per second, which outperforms other works in the literature after being normalized by the MIMO dimension.

A 2×2–8×8 sorted QR decomposition processor for MIMO detection

This study presents a joint QR decomposition and lattice reduction processor for 8×8 multiple-input multiple-output (MIMO) systems. The proposed algorithm enhances the BER performance by lattice reduction and reduces the hardware cost by sharing computation units and removing redundant operations. This processor can be reconfigured as three different modes, including joint QR decomposition and lattice reduction, lattice reduction, and QR decomposition. The proposed processor was implemented in TSMC 90nm 1P9M CMOS technology. The maximum throughput is 1.1 M matrix/s for QR decomposition, and 0.5 M matrix/s for the lattice reduction, and 0.33 M matrix/s for the joint QR decomposition and lattice reduction at a power consumption of 31.2 mW. The energy efficiency achieves 0.18nJ/matrix for the 8×8 MIMO preprocessing including both QR decomposition and lattice reduction.

Jhong-Yu Wang

Papers

A 3.1 Gb/s 8 $\,\times\,$ 8 Sorting Reduced K-Best Detector With Lattice Reduction and QR Decomposition

A 2×2–8×8 sorted QR decomposition processor for MIMO detection

A 0.18nJ/Matrix QR decomposition and lattice reduction processor for 8×8 MIMO preprocessing