High Efficiency Video Coding, the latest video standard, uses larger and variable-sized coding units and longer interpolation filters than H.264/AVC to better exploit redundancy in video signals. These algorithmic techniques enable a 50% decrease in bitrate at the cost of computational complexity, external memory bandwidth, and, for ASIC implementations, on-chip SRAM of the video codec. This paper describes architectural optimizations for an HEVC video decoder chip. The chip uses a two-stage subpipelining scheme to reduce on-chip SRAM by 56 kbytes-a 32% reduction. A high-throughput read-only cache combined with DRAM-latency-aware memory mapping reduces DRAM bandwidth by 67%. The chip is built for HEVC Working Draft 4 Low Complexity configuration and occupies 1.77 mm2 in 40-nm CMOS. It performs 4K Ultra HD 30-fps video decoding at 200 MHz while consuming 1.19 nJ/pixel of normalized system power.

A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications

The increased resolution of Quad Full High Definition (QFHD) offers significantly enhanced visual experience. However, the corresponding huge data throughput of up to 530 Mpixels/s greatly challenges the design of real-time video decoder VLSI with the extensive requirement on both DRAM bandwidth and computational power. In this work, a lossless frame recompression technique and a partial MB reordering scheme are proposed to save the DRAM access of a QFHD video decoder chip. Besides, pipelining and parallelization techniques such as NAL/slice-parallel entropy decoding are implemented to efficiently enhance its computational power. The chip supporting H.264/AVC high profile is fabricated in 90 nm CMOS and verified. It delivers a maximum throughput of 4096×2160@60fps, which is at least 4.3 times higher than the state-of-the-art. DRAM bandwidth requirement is reduced by typically 51%, which fits the design into a 64-bit LPDDR SDRAM interface and results in 58% DRAM power saving. Meanwhile, the core energy is saved by 54% by pipelining and parallelization.

A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip

With advances in video coding technology, two main streams of multimedia applications are emerging. The first involves more vivid perceptual experience and is leading to the next generation of TV specifications - Quad Full HD (QFHD, 4096×2160p) and 3D/multi-view TV. The second is the scalable broadcasting and streaming of video.

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A 59.5mW scalable/multi-view video decoder chip for Quad/3D Full HDTV and video streaming applications

3840 × 2160 and 7680 × 4320 UHDTV formats deliver remarkably enhanced visual experience relative to high definition but in the meanwhile involve huge complexity and memory bandwidth requirements in video encoding. Especially, enlarged motion distances of UHDTV lead to additional difficulties in the implementation of motion estimation, which is originally the most critical bottleneck of an encoder. This paper presents a motion estimation processor design for H.264/AVC. A test chip is implemented in 40 nm CMOS. With algorithm and architecture co-optimization, the processor delivers a maximum throughput of 1.59 Gpixel/s for 7680 × 4320 48 fps video, at least 7.5 times faster than previous designs. The corresponding core power dissipation is 622 mW at 210 MHz, with energy efficiency improved by at least 23%. The chip's DRAM bandwidth requirement is also 68% lower than previous chips. With a maximum search range of ±211 (horizontal) by ±106 (vertical) around a predictive search center, the proposed motion estimation processor well accommodates the high motion of UHDTV.

A 1.59 Gpixel/s Motion Estimation Processor With $-$ 211 to +211 Search Range for UHDTV Video Encoder

Video streaming has become the most common application in handhelds and this trend is expected to grow in future to account for about 75% of all mobile data traffic by 2021. Thus, optimizing the performance and energy consumption of video processing in mobile devices is critical for sustaining the handheld market growth. In this paper, we propose three complementary techniques, race-to-sleep, content caching and display caching, to minimize the energy consumption of the video processing flows. Unlike the state-of-the-art frame-by-frame processing of a video decoder, the first scheme, race-to-sleep, uses two approaches, called batching of frames and frequency boosting to prolong its sleep state for saving energy, while avoiding any frame drops. The second scheme, content caching, exploits the content similarity of smaller video blocks, called macroblocks, to design a novel cache organization for reducing the memory pressure. The third scheme, in turn, takes advantage of content similarity at the display controller to facilitate display caching further improving energy efficiency. We integrate these three schemes for developing an end-to-end video processing framework and evaluate our design on a comprehensive mobile system design platform with a variety of video processing workloads. Our evaluations show that the proposed three techniques complement each other in improving performance by avoiding frame drops and reducing the energy consumption of video streaming applications by 21%, on average, compared to the current baseline design.CCS CONCEPTS• Human-centered computing $ \rightarrow$ Mobile computing;• Computer systems organization $ \rightarrow$ Architectures; Embedded hardware;

Race-to-sleep + content caching + display caching: a recipe for energy-efficient video streaming on handhelds

An H.264/AVC HP video decoder is implemented in 90nm CMOS. Its maximum throughput reaches 4096×2160@60fps, which is at least 4.3x higher than the state-of-the-art. By using partial MB reordering and lossless frame recompression, 51% of DRAM bandwidth is reduced which results in 58% DRAM power saving. Meanwhile, various efficient parallelization techniques contribute to a core energy saving of 54%.

A 530Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip

In this paper, we present a video decoder chip for H.264/AVC high profile, MPEG-1/2 main profile and AVS Jprofile, which is capable of 60fps 1080p decoding at 200MHz. By applying a dedicated DRAM sub-system and a 2-D cache architecture, 50% of pins for DRAM connection and 36% of power consumption are saved, compared to state-of-the-art work in a system perspective. Meanwhile, 38% of gate count is reduced by applying resource sharing architectures between the 3 supported video formats.

A 1080p@60fps multi-standard video decoder chip designed for power and cost efficiency in a system perspective

In this paper, we presented an SoC based HW/SW co-design architecture for multi-standard audio decoding It is developed to support the audio standards of AAC LC profile, Dolby AC3, Ogg Vorbis, MPEG-1 Layer 3 (MP3) and Windows Media Audio (WMA) A VLSI reconfigurable filterbank based on CORDIC algorithm is developed to accelerate the multi-standard decoding process We designed and implemented an SoC platform to verify the interbank as an IP core Experimental result shows that the architecture is able to perform real-time audio decoding at low frequency (typically 106MHz for AAC and 113 MHz for MP3) and the implementation cost is low (443k gates, 34k bytes RAM and 45k bytes data ROM for 5 audio standards) The architecture is also flexible for extending support of new formats and standards

An SoC based HW/SW co-design architecture for multi-standard audio decoding

The invention discloses an addressing module structure for realizing a digital signal processor in the field of computer system structures. The addressing module structure comprises an address computation unit and an addressing register file which is connected with the address computation unit, wherein the address computation unit outputs an updated address to the addressing register file and receives a current address and a control signal. The addressing module structure can finish computation of the address within a clock period, have extremely-low circuit delay and meet a requirement of a high-performance signal processor on a high-operation speed.

Ji Kong

Papers

A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip

A 530Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip

A 1080p@60fps multi-standard video decoder chip designed for power and cost efficiency in a system perspective

An SoC based HW/SW co-design architecture for multi-standard audio decoding

Addressing module structure for realizing digital signal processor