Wide-bandgap (WBG) power semiconductor devices have become increasingly popular due to their superior characteristics compared to their Si counterparts. However, their fast switching speed and the ability to operate at high frequencies brought new challenges, among which the electromagnetic interference (EMI) is one of the major concerns. Many works investigated the structures of WBG power devices and their switching performance. In some cases, the conductive or radiated EMI was measured. However, the EMI-related topics, including their influence on noise sources, noise propagation paths, EMI reduction techniques, and EMC reliability issues, have not yet been systematically summarized for WBG devices. In this article, the literature on EMI research in power electronics systems with WBG devices is reviewed. Characteristics of WBG devices as EMI noise sources are reviewed. EMI propagation paths, near-field coupling, and radiated EMI are surveyed. EMI reduction techniques are categorized and reviewed. Specifically, the EMI-related reliability issues are discussed, and solutions and guidelines are presented.

A Survey of EMI Research in Power Electronics Systems With Wide-Bandgap Semiconductor Devices

SiC devices are promising for outperforming Si counterparts in high-frequency applications due to its superior material properties. Conventional wirebonded packaging scheme has been one of the most preferred package structures for power modules. However, the technique limits the performance of a SiC power module due to parasitic inductance and heat dissipation issues that are inherent with aluminum wires. In this article, low parasitic inductance and high-efficient cooling interconnection techniques for Si power modules, which are the foundation of packaging methods of SiC ones, are reviewed first. Then, attempts on developing packaging techniques for SiC power modules are thoroughly overviewed. Finally, scientific challenges in the packaging of SiC power module are summarized.

/pdf/review-of-packaging-schemes-for-power-module-1bxfgdpj20.pdf

Review of Packaging Schemes for Power Module

Power devices based on wide-bandgap material such as silicon carbide (SiC) can operate at higher switching speeds, higher voltages, and higher temperatures compared to those based on silicon material. This article highlights some opportunities brought by SiC devices in existing and emerging applications in terms of efficiency and power density improvement. While the opportunities are clear, there are also design challenges that must be met in order to realize their full potential. For example, the fast switching speeds and high dv/dt of SiC devices can cause increased electromagnetic interference, current overshoot, cross-talk effect, and have a negative impact on loads such as motors. This article presents several potential solutions to tackle the application challenges and to fully exploit the superior characteristics of SiC devices and converters while attenuating their negative side effects. This article provides an overview of recent SiC device research and development activities based on academic literature, work carried out by the authors and collaborators as well as input from industry. It aims to provide benchmark results and a timely and useful reference to accelerate the adoption and deployment of SiC devices and converters.

/pdf/opportunities-challenges-and-potential-solutions-in-the-2i3vgrlfg4.pdf

Opportunities, Challenges, and Potential Solutions in the Application of Fast-Switching SiC Power Devices and Converters

The crosstalk voltage on the gate-source terminal of SiC power mosfet s in a phase-leg circuit is composed of the gate–drain capacitor introduced voltage and the common-source inductor introduced voltage. The mathematical model of the crosstalk voltage indicates that to suppress two types of crosstalk voltage, there exists a contradictory requirement on the off -state gate loop impedance. This challenge reduces the effectiveness of conventional crosstalk elimination methods. As an improvement, a crosstalk voltage suppression circuit that synchronously eliminates the crosstalk voltage of gate–drain capacitance and the common-source inductance is proposed. In this article, instead of creating low-impedance gate loop in the off -state, a high-impedance gate loop is formatted to eliminate the voltage drop on the common-source inductance. Meanwhile, the potential false turn- on or the negative voltage spikes caused by gate–drain capacitance is eliminated by the precharge voltage in the gate-source capacitor. The required prestored charge is analyzed considering the nonlinear behavior of the junction capacitance of the SiC mosfet s. The proposed gate driver is experimentally verified in different switching conditions.

High Off-State Impedance Gate Driver of SiC MOSFETs for Crosstalk Voltage Elimination Considering Common-Source Inductance

Featuring higher switching speed and lower losses, the silicon carbide MOSFETs (SiC MOSFETs) are widely used in higher power density and higher efficiency power electronic applications as a new solution. Due to the limited current capability of a single module, more modules parallel-connected are necessary for higher power application. However, current sharing is the key obstacle. In this article, an active gate driver (AGD) for high-power SiC MOSFETs is presented to balance the currents of parallel-connected SiC MOSFET modules. The principle of the AGD is based on dynamic gate drive voltage adjustment to synchronize current edges and current slopes among parallel-connected SiC MOSFET modules automatically. Each AGD measures and controls the current of its SiC MOSFET module individually. No extra supervising control circuit is needed. In addition, the hardware and software configurations are independent of the system design and no restrictions on the number of SiC MOSFET modules connected in parallel exist. Finally, the switching performance of the AGD was experimentally verified on two parallel-connected SiC MOSFET modules in a multipulse test under constant and variable load currents. In addition, the effectiveness of AGD under different control topologies has been studied with simulation and verified using three parallel-connected SiC MOSFET modules.

Active Gate Driver for Improving Current Sharing Performance of Paralleled High-Power SiC MOSFET Modules

The higher voltage blocking capability and faster switching speed of silicon-carbide (SiC) mosfet s have the potential to replace Si insulated gate bipolar transistors (IGBTs) in medium-/low-voltage and high-power applications. In this paper, a state-of-the-art commercially available 325 A, 1700 V SiC mosfet module has been fully characterized under various load currents, bus voltages, and gate resistors to reveal their switching capability. Meanwhile, Si IGBT modules with similar power ratings are also tested under the same conditions. From the test results, several interesting points have been obtained: different to the Si IGBT module, the over-shoot current of the SiC mosfet module increases linearly with the increase of the load current and it has been explained by a model of the over-shoot current proposed in this paper; the induced negative gate voltage due to the complementary device turn- off (crosstalk effect) is more harmful to the SiC mosfet module than the induced positive gate voltage during turn- on when the gate off-voltage is –6 V; the maximum dv / dt and di / dt (electromagnetic interference) during switching transients of the SiC mosfet module are close to those of the Si IGBT module when the gate resistance is larger than 8 Ω but the switching loss of the SiC mosfet module is much smaller; the switching losses of the Si IGBT module are greater than those of the SiC mosfet module even when the gate resistance of the former is reduced to zero. An accurate power loss model, which is suitable for a three-phase two-level converter based on SiC mosfet modules considering the power loss of the parasitic capacitance, has been presented and verified in this paper. From the model, a 96.2% efficiency can be achieved at the switching frequency of 80 kHz and the power of 100 kW.

Performance Evaluation of High-Power SiC MOSFET Modules in Comparison to Si IGBT Modules

Efficiency, power quality, and reliability of SiC MOSFET-based voltage-source converters are significantly affected by the dead-time settings. The conventional fixed dead-time setting can induce large output voltage loss and additional energy loss due to the output capacitance of the SiC MOSFETs and the SiC Schottky barrier diodes or the freewheeling of the diodes, which will be more serious under high switching frequencies. This paper analyzes and models the detailed switching process of the SiC MOSFET half-bridge circuit when various dead-time settings are adopted. Based on the models, an optimal asymmetric variable dead-time (OAVDT) setting is proposed, which can avoid the discharging loss of the output capacitance and redundant freewheeling loss of the diode. The OAVDT setting is realized by adjusting the optimal dead-time in real time after the active device is turned off , which does not require any additional hardware circuits. The OAVDT setting can also reduce the output voltage loss to a certain level compared to the fixed dead-time setting. A three-phase two-level SiC MOSFET inverter has been built in the lab to verify the proposed OAVDT setting. Experimental results show a decrease of power loss by 22.5% with reduced output voltage loss compared to the fixed dead-time setting of 0.28 μs when the output power is 8 kW and the switching frequency is 40 kHz. The proposed OAVDT setting shows clear advantages over that of fixed dead-time setting, especially at light load and high switching frequencies.

Modeling and Implementation of Optimal Asymmetric Variable Dead-Time Setting for SiC MOSFET-Based Three-Phase Two-Level Inverters

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) three-phase two-level converter dead zone setting method. The method comprises the following steps: acquiring an output current of a midpoint of each phase of bridge arm; judging the polarity of the output current, and determining the initiative of an upper-bridge switching tube and a lower-bridge switching tube of the phase of bridge arm according to the polarity of the output current; acquiring parameter information of an SiC MOSFET and a driver board thereof, and calculating pre-dead time and post-deadtime according to the parameter information; setting the dead time before an active switching tube is turned on to be N times of the pre-dead time, wherein N is greater than 1.5 but less than 2.5; setting a current upper limit value and a current lower limit value, and calculating the minimum dead time and the maximum dead time according to the current upper limit value and the current lower limitvalue; and comparing an absolute value of the output current with an absolute value of the current upper limit value and an absolute value of the current lower limit value, and setting the dead timeafter the active switching tube is turned off as the post-dead time, the minimum dead time and the maximum dead time according to a comparison result.

SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) three-phase two-level converter dead zone setting method

A tomographic microscopy system can achieve instantaneous three-dimensional imaging, and this type of microscopy system has been widely used in the study of biological samples; however, existing chromatographic microscopes based on off-axis Fresnel zone plates have degraded image quality due to geometric aberrations such as spherical aberration, coma aberration, and image scattering. This issue hinders the further development of chromatographic microscopy systems. In this paper, we propose a method for the design of an off-axis Fresnel zone plate with the elimination of aberrations based on double exposure point holographic surface interference. The aberration coefficient model of the optical path function was used to solve the optimal recording parameters, and the principle of the aberration elimination tomography microscopic optical path was verified. The simulation and experimental verification were carried out utilizing a Seidel coefficient, average gradient, and signal-to-noise ratio. First, the aberration coefficient model of the optical path function was used to solve the optimal recording parameters. Then, the laminar mi-coroscopy optical system was constructed for the verification of the principle. Finally, the simulation calculation results and the experimental results were verified by comparing the Seidel coefficient, average gradient, and signal-to-noise ratio of the microscopic optical system before and after the aberration elimination. The results show that for the diffractive light at the orders 0 and ±1, the spherical aberration W040 decreases by 62–70%, the coma aberration W131 decreases by 96–98%, the image dispersion W222 decreases by 71–82%, and the field curvature W220 decreases by 96–96%, the average gradient increases by 2.8%, and the signal-to-noise ratio increases by 18%.

https://www.mdpi.com/1424-8220/22/3/1113/pdf?version=1643707445

Study of the Off-Axis Fresnel Zone Plate of a Microscopic Tomographic Aberration

/pdf/analysis-of-synchronous-rectification-discontinuous-pwm-for-3aic7nfhgu.pdf

Jiahang Zhang

Papers

Performance Evaluation of High-Power SiC MOSFET Modules in Comparison to Si IGBT Modules

Modeling and Implementation of Optimal Asymmetric Variable Dead-Time Setting for SiC MOSFET-Based Three-Phase Two-Level Inverters

SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) three-phase two-level converter dead zone setting method

Study of the Off-Axis Fresnel Zone Plate of a Microscopic Tomographic Aberration

Analysis of Synchronous Rectification Discontinuous PWM for SiC MOSFET Three Phase Inverters