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Design Of Analog Cmos Integrated Circuits

Image sensors with internal computing capability enable in-sensor computing that can significantly reduce the communication latency and power consumption for machine vision in distributed systems and robotics. Two-dimensional semiconductors have many advantages in realizing such intelligent vision sensors because of their tunable electrical and optical properties and amenability for heterogeneous integration. Here, we report a multifunctional infrared image sensor based on an array of black phosphorous programmable phototransistors (bP-PPT). By controlling the stored charges in the gate dielectric layers electrically and optically, the bP-PPT's electrical conductance and photoresponsivity can be locally or remotely programmed with 5-bit precision to implement an in-sensor convolutional neural network (CNN). The sensor array can receive optical images transmitted over a broad spectral range in the infrared and perform inference computation to process and recognize the images with 92% accuracy. The demonstrated bP image sensor array can be scaled up to build a more complex vision-sensory neural network, which will find many promising applications for distributed and remote multispectral sensing. 

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Programmable black phosphorus image sensor for broadband optoelectronic edge computing

Image sensors with internal computing capability enable in-sensor computing that can significantly reduce the communication latency and power consumption for machine vision in distributed systems and robotics. Two-dimensional semiconductors are uniquely advantageous in realizing such intelligent visionary sensors because of their tunable electrical and optical properties and amenability for heterogeneous integration. Here, we report a multifunctional infrared image sensor based on an array of black phosphorous programmable phototransistors (bP-PPT). By controlling the stored charges in the gate dielectric layers electrically and optically, the bP-PPT's electrical conductance and photoresponsivity can be locally or remotely programmed with high precision to implement an in-sensor convolutional neural network (CNN). The sensor array can receive optical images transmitted over a broad spectral range in the infrared and perform inference computation to process and recognize the images with 92% accuracy. The demonstrated multispectral infrared imaging and in-sensor computing with the black phosphorous optoelectronic sensor array can be scaled up to build a more complex visionary neural network, which will find many promising applications for distributed and remote multispectral sensing.

Neuro-inspired deep learning algorithm has shown promising futures for artificial intelligence (AI). Despite the remarkable progress on software-based neural network, the traditional von-Neumann hardware architecture has suffered from limited energy efficiency while facing unprecedented large amount of data. In order to meet the performance requirement of neuro-inspired computing, the large-scale vector-matrix multiplication is preferred to be performed in-situ, namely compute-in-memory (CIM). Non-volatile memory devices with different materials have been proposed for weight storage as synaptic devices. Among them, the HfO2-based ferroelectric devices have obtained great attention because of their low energy consumption, good CMOS compatibility and multi-bit per cell potential. In this review, recent trends and prospects of the ferroelectric synaptic devices are surveyed. First, we present the three-terminal synaptic devices based on ferroelectric field effect transistor (FeFET), and discuss the switching physics of the intermediate states, the back-end-of-line (BEOL) integration and the 3D NAND architecture design. Then, we introduce hybrid precision synapse concept that leverages the volatile charges on the gate capacitor of FeFET and the non-volatile polarization on the gate dielectric of FeFET. Lastly, we review two-terminal synaptic devices using ferroelectric tunnel junction (FTJ) and ferroelectric capacitor (FeCAP). Design margins of the crossbar array with FTJ and FeCAP are analyzed.

Ferroelectric HfO2-based synaptic devices: recent trends and prospects

Since our demonstration of unsupervised learning using the CMOS-only charge-trap transistors (CTTs) as analog synapses, there has been an increasing interest in exploiting the device for various other neural network (NN) applications. However, most of these studies are limited to mere simulation due to the absence of detailed experimental device characterization. In this article, we provide a comprehensive investigation of the programming behavior of CTTs, including analog retention, intra- and inter-device variation, and fine-tuning of the device, both for individual devices and for devices in an integrated array. It is found that, after programming, the channel current gradually increases to a higher level, and the shift is larger when the device is programmed to a higher threshold voltage. With this postprogramming current increase appropriately accounted for, individual devices can be programmed to an equivalent precision of five bits, and three bits can be achieved for devices in an array. Our results reveal the promising future of using the CTT as a CMOS-only analog memory device.

Charge-Trap Transistors for CMOS-Only Analog Memory

An analog neural network computing engine based on CMOS-compatible charge-trap transistor (CTT) is proposed in this paper. CTT devices are used as analog multipliers. Compared to digital multipliers, CTT-based analog multiplier shows significant area and power reduction. The proposed computing engine is composed of a scalable CTT multiplier array and energy efficient analog–digital interfaces. By implementing the sequential analog fabric, the engine’s mixed-signal interfaces are simplified and hardware overhead remains constant regardless of the size of the array. A proof-of-concept 784 by 784 CTT computing engine is implemented using TSMC 28-nm CMOS technology and occupies 0.68 mm2. The simulated performance achieves 76.8 TOPS (8-bit) with 500 MHz clock frequency and consumes 14.8 mW. As an example, we utilize this computing engine to address a classic pattern recognition problem—classifying handwritten digits on MNIST database and obtained a performance comparable to state-of-the-art fully connected neural networks using 8-bit fixed-point resolution.

An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT)

An analog neural network computing engine based on CMOS-compatible charge-trap transistor (CTT) is proposed in this paper. CTT devices are used as analog multipliers. Compared to digital multipliers, CTT-based analog multiplier shows significant area and power reduction. The proposed computing engine is composed of a scalable CTT multiplier array and energy efficient analog-digital interfaces. Through implementing the sequential analog fabric (SAF), the engine mixed-signal interfaces are simplified and hardware overhead remains constant regardless of the size of the array. A proof-of-concept 784 by 784 CTT computing engine is implemented using TSMC 28nm CMOS technology and occupied 0.68mm2. The simulated performance achieves 76.8 TOPS (8-bit) with 500 MHz clock frequency and consumes 14.8 mW. As an example, we utilize this computing engine to address a classic pattern recognition problem -- classifying handwritten digits on MNIST database and obtained a performance comparable to state-of-the-art fully connected neural networks using 8-bit fixed-point resolution.

An Analog Neural Network Computing Engine using CMOS-Compatible Charge-Trap-Transistor (CTT)

The present invention provides a memory unit and a method for controlling the memory unit The memory cell includes a first charge storage transistor and a second charge storage transistor The firstcharge storage transistor includes a substrate, a first end is coupled to a first bit line, a second end is coupled to a signal line, a control end is coupled to a word line, and a dielectric layer isformed between the substrate of the first charge storage transistor and the control terminal of the first charge storage transistor The second charge storage transistor includes a substrate, a firstend is coupled to the signal line, a second end is coupled to the second bit line, and a control end is coupled to the word line The dielectric layer is formed between the substrate of the second charge storage transistor and the control end of the second charge storage transistor The invention can effectively reduce the size of integrated circuits in applications, and can be applied to integrated circuit chips that require lower power consumption

Memory unit and method for controlling memory unit

A convolution operation device includes a convolution operation module, a memory, a scale control module and a scaling unit. The convolution operation module outputs a plurality of convolution operation results containing fractional parts. The memory is coupled to the convolution operation module for receiving and storing the convolution operation results containing the fractional parts, and outputs a plurality of convolution operation input values containing fractional parts. The scale control module is coupled to the convolution operation module and generates a scaling signal according to a total scale of the convolution operation results containing the fractional parts. The scaling unit is coupled to the memory, the scale control module, and the convolution operation module, adjusts the scale of the convolution operation input values containing the fractional parts according to the scaling signal, and outputs the adjusted convolution operation input values containing the fractional parts to the convolution operation module.

Convolution operation device and method of scaling convolution input for convolution neural network

A memory cell includes a first charge trap transistor and a second charge trap transistor. The first charge trap transistor has a substrate, a first terminal coupled to a first bitline, a second terminal coupled to a signal line, a control terminal coupled to a wordline, and a dielectric layer formed between the substrate of the first charge trap transistor and the control terminal of the first charge trap transistor. The second charge trap transistor has a substrate, a first terminal coupled to the signal line, a second terminal coupled to a second bitline, a control terminal coupled to the wordline, and a dielectric layer between the substrate of the second charge trap transistor and the control terminal of the second charge trap transistor. Charges are either trapped to or detrapped from the dielectric layer of the first charge trap transistor when writing data to the memory cell.

Jiang Ming-Zhe

Papers

An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT)

An Analog Neural Network Computing Engine using CMOS-Compatible Charge-Trap-Transistor (CTT)

Memory unit and method for controlling memory unit

Convolution operation device and method of scaling convolution input for convolution neural network

Memory cell with charge trap transistors and method thereof capable of storing data by trapping or detrapping charges