A digital gate driver (DGD) is an important technology to reduce both switching loss and voltage and/or current overshoot. In this paper, a 5 V, 300 MSa/s, 6-bit DGD IC, where the gate current is varied in 64 levels for each of 16 3.3-ns time intervals, is developed using 180-nm BCD process for GaN FETs. The parameters for DGD are automatically optimized using a simulated annealing algorithm through repeated switching measurements. In the turn-on of GaN FETs at 48 V and 8 A, compared with the conventional single-step gate driving, the proposed gate drive using DGD reduces the switching loss from 3.9 μJ to 1.2 μJ by 69 % at the same the current overshoot of 3.4 A and reduces the current overshoot from 8.5 A to 3.4 A by 60 % at the same switching loss of 1.2 μJ, which clearly shows the advantage of DGD for GaN FETs.

5 V, 300 MSa/s, 6-bit Digital Gate Driver IC for GaN Achieving 69 % Reduction of Switching Loss and 60 % Reduction of Current Overshoot

A single-input, dual-output (SIDO) digital gate driver (DGD) IC, integrating two 6-bit DGDs, two current sensors, and a controller, is proposed to equalize the drain current (ID) variation of two parallel-connected SiC MOSFETs. The DC and surge components of ID of each MOSFET are equalized by digitally controlling the gate voltage amplitude and the gate current at turn-on, respectively. In the double pulse test at 300 V and 40 A using two parallel SiC MOSFETs with different threshold voltages of 0.5 V, the proposed SIDO DGD IC reduces the differences in the DC and surge components of ID of the two MOSFETs from 2.6 A to 0.13 A by 95 % and from 1.9 A to 0.32 A by 83 %, respectively. The automatic equalization of the DC components of ID of the two MOSFETs using SIDO DGD IC is also successfully demonstrated.

Equalization of DC and Surge Components of Drain Current of Two Parallel-Connected SiC MOSFETs Using Single-Input Dual-Output Digital Gate Driver IC

An 8-bit digital gate driver (DGD) using a half-bridge digital-to-analog converter (HB DAC) IC and two power MOSFETs is proposed to enable the output voltage swing of ± 15 V and the large gate current up to 58 A for a 6500 V, 1000 A IGBT module. In the turn-on measurements of IGBT at 3000 V and 1000 A, compared with the conventional single-step gate driving, the proposed active gate driving using DGD reduces the switching loss from 6.9 J to 4.8 J by 30 % at the same current overshoot of 1.3 kA and reduces the current overshoot from 1560 A to 1330 A by 15 % at the same switching loss of 5 J, which clearly shows the advantage of DGD for the 6500 V, 1000 A IGBT module. This paper is the first to demonstrate the advantages of DGD in the high-voltage, large-current IGBT modules.

Large Current Output Digital Gate Driver Using Half-Bridge Digital-to-Analog Converter IC and Two Power MOSFETs

A single-input, dual-output (SIDO) digital gate driver (DGD) IC, integrating two 6-bit DGDs, two current sensors, and a controller, is proposed to equalize the drain current (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</inf> ) variation of two parallel-connected SiC MOSFETs. The DC and surge components of I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</inf> of each MOSFET are equalized by digitally controlling the gate voltage amplitude and the gate current at turn-on, respectively. In the double pulse test at 300 V and 40 A using two parallel SiC MOSFETs with different threshold voltages of 0.5 V, the proposed SIDO DGD IC reduces the differences in the DC and surge components of I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</inf> of the two MOSFETs from 2.6 A to 0.13 A by 95 % and from 1.9 A to 0.32 A by 83 %, respectively. The automatic equalization of the DC components of I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</inf> of the two MOSFETs using SIDO DGD IC is also successfully demonstrated. 

An 8-bit digital gate driver (DGD) using a half-bridge digital-to-analog converter (HB DAC) IC and two power MOSFETs is proposed to enable the output voltage swing of ± 15 V and the large gate current up to 58 A for a 6500 V, 1000 A IGBT module. In the turn-on measurements of IGBT at 3000 V and 1000 A, compared with the conventional single-step gate driving, the proposed active gate driving using DGD reduces the switching loss from 6.9 J to 4.8 J by 30 % at the same current overshoot of 1.3 kA and reduces the current overshoot from 1560 A to 1330 A by 15 % at the same switching loss of 5 J, which clearly shows the advantage of DGD for the 6500 V, 1000 A IGBT module. This paper is the first to demonstrate the advantages of DGD in the high-voltage, large-current IGBT modules. 

Active gate driving of power devices seeks to shape switching trajectories via the gate, for example, to reduce EMI without degrading efficiency. To this end, driver ICs with integrated arbitrary waveform generators have been used to achieve complex gate signals. This article describes, for the first time, the implementation details of a digitally programmable arbitrary waveform gate driver capable of a 10-GHz waypoint rate, including comprehensive design considerations for critical high-speed subsystems that codify the tradeoff in flexibility, speed, and area. The design, which is taped out in a 180-nm high-voltage CMOS process, utilizes buffers that switch up to ten times in a single clock cycle to overcome the limited achievable clock speed of high-voltage silicon integrated circuits and a fully digital architecture to provide robustness under high slew rates of the ground rail. The driver IC has networks of 100-ps delay elements that are configured prior to a switching transient, to selectively control an array of fast, parallel-connected drivers with different output impedances. Key to the high timing resolution are high-speed asynchronous circuits for memory readout, output buffering, and pulse generation. The driver IC is experimentally evaluated to have a 100-ps resolution and to operate reliably in a 400-V gallium nitride (GaN) bridge leg, under ground-rail voltage slew rates peaking at over 100 V/ns. Design rules are provided to obtain an architecture with the least area for a given set of timing and impedance resolution requirements. The reported design methods enable complex driving waveforms to be applied during nanosecond-scale transients of GaN power devices and demonstrate how digitally programmable active gate drivers for GaN power FETs can be designed to meet a given set of application requirements.

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Jianjing Wang

Papers

Full Custom Design of an Arbitrary Waveform Gate Driver With 10-GHz Waypoint Rates for GaN FETs