Jin-Wook Lee

TL;DR: In this article, the authors proposed a method for providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of the active regions, where each of the first gate line and second gate line crossing at least one active region.

TL;DR: A 116.7-mm/sup 2/ NAND flash memory having two modes, 1-Gb multilevel program cell (MLC) and high-performance 512-Mb single-level program Cell (SLC) modes, is fabricated with a 0.15-/spl mu/m CMOS technology, achieving 1.6 and 6.9 MB/s program throughputs for MLC and SLC modes.

TL;DR: A 1 Gb NAND flash memory with 2b per cell uses 0.15 /spl mu/m CMOS and achieves simultaneous operation of 4 independent banks with 1.6 GMB/s program throughput.

TL;DR: In this article, a system for managing an object base on a criterion in a display environment, including a condition analysis unit which selects the object having metadata information corresponding to condition information of the criterion, is presented.

TL;DR: In this paper, a flash memory device includes a memory cell array having a first region and a second region that include memory cells arranged in a plurality of rows and columns; an address storage circuit adapted to store address information for defining the second region; a row decoder and a control logic adapted to control the voltage generating circuit in response to an output of the detecting circuit during read operation.