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Design Of Analog Cmos Integrated Circuits

Presentacio sobre l'Oficina de Proteccio de Dades Personals de la UAB i la politica Open Science. Va formar part de la conferencia "Les politiques d'Open Data / Open Acces: Implicacions a la recerca" orientada a investigadors i gestors de projectes europeus que va tenir lloc el 20 de setembre de 2018 a la Universitat Autonoma de Barcelona

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General data protection regulation

Near infrared spectroscopy: A mature analytical technique with new perspectives - A review.

Precision amplifiers dominate the power dissipation in most high-speed pipelined analog-to-digital converters (ADCs). We propose a digital background calibration technique as an enabling element to replace precision amplifiers by simple power-efficient open-loop stages. In the multibit first stage of a 12-bit 75-MSamples/s proof-of-concept prototype, we achieve more than 60% residue amplifier power savings over a conventional implementation. The ADC has been fabricated in a 0.35-/spl mu/m double-poly quadruple-metal CMOS technology and achieves typical differential and integral nonlinearity within 0.5 LSB and 0.9 LSB, respectively. At Nyquist input frequencies, the measured signal-to-noise ratio is 67 dB and the total harmonic distortion is -74 dB. The IC consumes 290 mW at 3 V and occupies 7.9 mm/sup 2/.

A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification

Reactive matching is extended to wide bandwidths using the impedance property of LC-ladder filters. In this paper, we present a systematic method to design wideband low-noise amplifiers. An SiGe amplifier with on-chip matching network spanning 3-10 GHz delivers 21-dB peak gain, 2.5-dB noise figure, and -1-dBm input IP3 at 5 GHz, with a 10-mA bias current.

A 3-10-Ghz low-noise amplifier with wideband LC-ladder matching network

This paper presents an innovative topology for an operational transconductance amplifier (OTA) based on a CMOS inverter topology. This OTA is proper for biomedical and healthcare circuits and systems, due to a low level of noise and power consumption, together with elevated gain. This is a fully-differential implementation, with a double CMOS branch biased by two pairs of voltage-combiners, in both NMOS and PMOS configurations, highly improving the gain and the gain-bandwidth product, improving the OTA energy-efficiency. An elevated figure-of-merit is achieved, i.e., a 1628 MHz×pF/mA, and a gain of 53 dB, under a voltage supply source of 2 V. The results are compared with state-of-the-art OTAs in this field of study and the potential is fully fulfilled with a state-of-the-art layout-aware optimization tool, AIDA, particularly important to overcome the device stacking problematic in lower supplies.

A Low Noise CMOS Inverter-Based OTA for and Healthcare Signal Receivers

This paper describes and compares some of the most energy and area efficient self-calibration techniques reported over the past years. Additional techniques used to further improve power dissipation are briefly described as well. A robust mixed-signal self-calibration technique is proposed, in which, the multi-bit first stage in the ADC is calibrated without requiring any modifications, as long as the ideal conversion characteristic of this stage is known. A novel Gaussian Noise Generator is used as the input analog stimulus and, on the digital side, the calibration algorithm does not require explicit multiplications, which greatly simplifies the digital circuitry. Experimental measurements of a 13-bit ADC fabricated in 90 nm CMOS, after calibration and at 40 MS/s, show that the SFDR is improved by over 14 dB (to 84 dB), the THD is improved by over 10 dB (to −80 dB), achieving a peak ENOB of 11.3 bits for a 10 MHz input and with a 1.2 V power supply.

Purely-digital versus mixed-signal self-calibration techniques in high-resolution pipeline ADCs

This paper presents a 1.5-bit MDAC circuit to be used in pipeline ADCs which employs a switched-current source to perform the reference shifting of the MDAC (the 1.5-bit digital-to-analog function). In the proposed circuit, the two single-ended reference voltage sources that are traditionally used (V REFP and V REFN ), are replaced by a switched-current source. To evaluate and compare the performance of the proposed circuit, two 10-bit 40 MS/s ADCs, one using the traditional switched-capacitor (SC) MDAC and the other using the proposed MDAC, are designed. Simulation results show that the performance of the ADC with the proposed MDAC is enhanced since the power needed for the current sources is smaller than the power supplied by the reference voltage sources. Moreover, the proposed circuit does not require any reference voltage buffer, which can be difficult to design with relatively low power dissipation.

Design of a 10-bit 40 MS/s pipelined ADC using 1.5-bit with current-mode reference shifting

The use of the dynamic threshold MOS (DTMOS) technique is evaluated in a two-stage rail-to-rail Input/Output, constant G m amplifier. The proper choice of specific transistors in which the technique should be used is presented, as well as the resulting improvements, mainly regarding stability of the circuit at low voltage operation. The DTMOS technique is used in the NMOS transistors of the folded-cascode input stage, allowing the circuit to be stable at V DD = 0.4 V, with equivalent gain and gain-and-bandwidth product (GBW) values achieved with the same V DD value, for the initial circuit operating at 0.8 V. The implemented changes allow the circuit to be stable at low voltage operations without requiring any increase in the cascoded-Miller compensation capacitors, saving circuit area and, consequently, cost.

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João Goes

Papers

A Low Noise CMOS Inverter-Based OTA for and Healthcare Signal Receivers

Purely-digital versus mixed-signal self-calibration techniques in high-resolution pipeline ADCs

Design of a 10-bit 40 MS/s pipelined ADC using 1.5-bit with current-mode reference shifting

Stability Improvements in a Rail-to-Rail Input/Output, Constant Gm Operational Amplifier, at 0.4 V Operation, Using the Low-Voltage DTMOS Technique

Ultra-low-voltage LNA with high gain and low noise figure