R
Ricardo Povoa
Researcher at Instituto Superior Técnico
Publications - 52
Citations - 490
Ricardo Povoa is an academic researcher from Instituto Superior Técnico. The author has contributed to research in topics: Amplifier & Topology (electrical circuits). The author has an hindex of 11, co-authored 48 publications receiving 345 citations. Previous affiliations of Ricardo Povoa include University of Lisbon.
Papers
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Journal ArticleDOI
AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation
TL;DR: AIDA is presented, an analog integrated circuit design automation environment, which implements a design flow from a circuit-level specification to physical layout description, and the integration of AIDA environment on the traditional analog IC design flow is discussed, and demonstrated.
Journal ArticleDOI
Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop
Ricardo Martins,Nuno Lourenço,Fábio Passos,Ricardo Povoa,Antonio Canelas,Elisenda Roca,Rafael Castro-Lopez,Javier Sieiro,Francisco V. Fernández,Nuno Horta +9 more
TL;DR: An analysis of the methodologies proposed in the past years to automate the synthesis of radio-frequency (RF) integrated circuit blocks is presented, and a multiobjective optimization-based layout-aware sizing approach with preoptimized integrated inductor(s) design space is proposed.
Journal ArticleDOI
Automatic synthesis of RF front-end blocks using multi-objective evolutionary techniques
TL;DR: An automatic synthesis of three typical blocks of nowadays RF front-end receivers, a narrowband differential low-noise amplifier, a mixer and a local oscillator, is presented, proving the surplus value of using an automatic IC design tool in RF circuitry synthesis.
Journal ArticleDOI
Floorplan-aware analog IC sizing and optimization based on topological constraints
TL;DR: This paper presents a methodology for analog IC circuit-level sizing and optimization, which takes into account the layout geometrical properties, by introducing a simple and general description that permits the inclusion of the floorplan generation in the sizing optimization loop with negligible computational costs.
Proceedings ArticleDOI
AIDA: Robust layout-aware synthesis of analog ICs including sizing and layout generation
TL;DR: This paper presents AIDA 2015, the newest version of AIDA, an analog integrated circuit design automation environment, which implements a design flow from a circuit-level specification to physical layout description, using state-of-the-art technologies.