The growing packing density and power consumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnections Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits The paper is concluded with an overview of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods

/pdf/thermal-modeling-analysis-and-management-in-vlsi-circuits-27gdag8m8n.pdf

Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods

This paper presents a new analytical propagation delay model for nanoscale CMOS inverters. By using a non-saturation current model, the analytical input-output transfer responses and propagation delay model are derived. The model is used for calculating inverter delays for different input transition times, load capacitances and supply voltages. Delays predicted by the proposed model are in good agreement with those of transistor level simulation results from SPICE, with accuracy of 3% or better.

/pdf/analytical-transient-response-and-propagation-delay-model-32uisehq1w.pdf

Analytical transient response and propagation delay model for nanoscale CMOS inverter

The growing packing density and power con- sumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers. The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnec- tions. Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues. This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits. The paper is concluded with an over- view of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods.

Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods Maximum chip performance under peak permissible temperature limits may be achieved with the help of combined electrical and thermal simulation of VLSI circuits.

Virtual Prototyping of Portable Mobile Communication System Based on ARMulator.

A Low Power Quaternary Interconnection with Synchronization

This paper presents a simple method to estimate short-circuit power dissipation for static CMOS logic circuits. Short-circuit current expression is derived by accurately interpolating peak points of actual current curves which is influenced by the gate-to-drain coupling capacitance. It is shown through simulations that the proposed technique yields better accuracy than previous methods when signal transition time and/or load capacitance decreases, which is a characteristic of the present technological evolution.

Jong-Humn Baek

Papers

Short circuit power estimation of static CMOS circuits

PCB Plane Modeling Technique using AC-Loss Model for Circuit Simulation