J
Jong-Pil Son
Researcher at Samsung
Publications - 55
Citations - 617
Jong-Pil Son is an academic researcher from Samsung. The author has contributed to research in topics: Semiconductor memory & Memory cell. The author has an hindex of 13, co-authored 55 publications receiving 541 citations.
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Patent
Magnetic devices and methods of fabricating the same
Jong-Pil Son,Sang-beom Kang +1 more
TL;DR: In this paper, a tunnel barrier pattern is interposed between a first magnetic pattern and a second magnetic pattern, and the central portion of the tunnel barrier has a substantially uniform thickness.
Proceedings ArticleDOI
25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications
Young-Cheon Kwon,Sukhan Lee,Jae-Hoon Lee,Sang-Hyuk Kwon,Je Min Ryu,Jong-Pil Son,O Seongil,Hak-soo Yu,Hae-Suk Lee,Soo-Young Kim,Young-min Cho,Jin Guk Kim,Jongyoon Choi,Hyun-Sung Shin,Jin Kim,Bengseng Phuah,Hyoung-Min Kim,Myeong Jun Song,Ahn Choi,Daeho Kim,SooYoung Kim,Eun-Bong Kim,Wang David T,Shin-haeng Kang,Yu-Hwan Ro,Seung-Woo Seo,Joon-Ho Song,Jae-Youn Youn,Kyomin Sohn,Nam Sung Kim +29 more
TL;DR: FIMDRAM as discussed by the authors integrates a 16-wide single-instruction multiple-data engine within the memory banks and exploits bank-level parallelism to provide $4 \times higher processing bandwidth than an off-chip memory solution.
Patent
Memory modules and memory systems
TL;DR: In this paper, the buffer chip selectively refreshes each of the plurality of groups in each of a plurality of refresh time regions that are periodically repeated and applies respective refresh periods to the plurality groups, respectively.
Journal ArticleDOI
A 0.31–1 GHz Fast-Corrected Duty-Cycle Corrector With Successive Approximation Register for DDR DRAM Applications
TL;DR: This brief presents a duty cycle corrector (DCC) using a binary search algorithm with successive approximation register (SAR) in order to achieve fast duty-correction with a small die area, a SAR-controller is exploited as a duty-Correction controller.
Patent
Semiconductor memory devices, memory systems including the same and methods of operating the same
TL;DR: In this article, a test circuit reads data stream from the memory cell array, configured to compare bits of each first unit in the data stream, compares corresponding bits in the first units as each second unit and outputs a fail information signal including pass/fail information on the data streams and additional information on data stream.