Seong-Jin Jang

TL;DR: In this article, the ability to repair defective cells in a memory array, by replacing those cells with redundant cells, is improved using a redundant memory line control circuit that employs two types of redundancy programming.

TL;DR: The proposed DBI circuit uses an analog majority voter insensitive to mismatch for small area and delay, and a dual duty cycle corrector (DCC) is used to reduce duty error and jitter by averaging two outputs of two DCCs.

TL;DR: In this article, a three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips, and I/O connections of slave chips need not be connected to channels on a motherboard.

TL;DR: Dual error detection scheme is proposed to guarantee the reliability of signals, and gain enhanced buffer and PVT tolerant data fetch scheme are adopted for CA and DQ respectively to reduce the output jitter.

TL;DR: A 1.0 V 8 Gbit LPDDR4 SDRAM with 3.2 Gbps/pin speed and integrated ECC engine for sub-1 V DRAM core is presented and the following IO features are introduced: Low voltage swing terminated logic drivers with VOH level calibration and periodic ZQ calibration, unmatched DQ/DQS scheme and DQS oscillator for D QS tree delay tracking.