IEEE International Solid-State Circuits Conference

A 60-GHz band, three-stage pseudo-differential power amplifier (PA) is implemented with input and output baluns on-chip. Each stage consists of a neutralized common-source amplifier pair. Neutralization mitigates the intrinsic gate-drain feedback of each transistor for increased power gain and reverse isolation. Shielded transformers couple the gain stages and allow low supply voltage operation. Fabricated in a 65-nm bulk CMOS process, the measured small-signal gain of the 0.13 × 0.41 mm2 PA is 16 dB at 60 GHz with 3-dB bandwidth more than 8.5 GHz, while consuming 50 mW from a 1-V supply. Reverse isolation is better than 42 dB from 55 to 65 GHz. Maximum saturated output power is 11.5 dBm with a peak PAE of 15.2% measured at 62 GHz; from 58 to 65 GHz, the measured PAE is above 10%.

A 58–65 GHz Neutralized CMOS Power Amplifier With PAE Above 10% at 1-V Supply

This paper presents a new approach for power amplifier design using deep submicron CMOS technologies. A transformer based voltage combiner is proposed to combine power generated from several low-voltage CMOS amplifiers. Unlike other voltage combining transformers, the architecture presented in this paper provides greater flexibility to access and control the individual amplifiers in a voltage combined amplifier. In this work, this voltage combining transformer has been utilized to control output power and improve average efficiency at power back-off. This technique does not degrade instantaneous efficiency at peak power and maintains voltage gain with power back-off. A 1.2 V, 2.4 GHz fully integrated CMOS power amplifier prototype was implemented with thin-oxide transistors in a 0.13 mum RF-CMOS process to demonstrate the concept. Neither off-chip components nor bondwires are used for output matching. The power amplifier transmits 24 dBm power with 25% drain efficiency at 1 dB compression point. When driven into saturation, it transmits 27 dBm peak power with 32% drain efficiency. At power back-off, efficiency is greatly improved in the prototype which employs average efficiency enhancement circuitry.

Fully Integrated CMOS Power Amplifier With Efficiency Enhancement at Power Back-Off

In recent years, there has been tremendous interest in trying to implement the power amplifier in CMOS, due to its cost and integration benefits. Most of the high power (watt-level) CMOS PAs reported to date have not exhibited sufficient linearity required for next generation wireless standards. In this paper, we report a single-chip linear CMOS PA with sufficient power and linearity for emerging OFDM-based 4G WiMAX applications. This 90 nm 2.4 GHz CMOS linear power amplifier uses a two-stage transformer-based power combiner and produces a saturated output power of 30.1 dBm with 33% PAE and 28 dB small-signal gain. A novel bypass network is introduced to ensure stability without sacrificing gain. The choice of optimal biasing and capacitive compensation produces very flat AM-AM and AM-PM response up to high power. The PA has been tested with OFDM modulated signal and produces EVM better than -25 dB at 22.7 dBm average power. Graceful power back-off is demonstrated through turning off one of the stages, allowing low-power operation with enhanced efficiency.

A Fully Integrated Dual-Mode Highly Linear 2.4 GHz CMOS Power Amplifier for 4G WiMax Applications

A transformer-based high-order output matching network is proposed for broadband power amplifier design, which provides optimum load impedance for maximum output power within a wide operating frequency range. A design methodology to convert a canonical bandpass network to the proposed matching configuration is also presented in detail. As a design example, a push-pull deep class-AB PA is implemented with a third-order output network in a standard 90 nm CMOS process. The leakage inductances of the on-chip 2:1 transformer are absorbed into the output matching to realize the third-order network with only two inductor footprints for area conservation. The amplifier achieves a 3 dB bandwidth from 5.2 to 13 GHz with 25.2 dBm peak and 21.6% peak PAE. The EVM for QPSK and 16-QAM signals both with 5 Msample/s are below 3.6% and 5.9% at the output 1 dB compression point. This verifies the PA's capability of amplifying a narrowband modulated signal whose center-tone can be programmed across a large frequency range. The measured BER for transmitting a truly broadband PRBS signal up to 7.5 Gb/s is less than 10 , demonstrating the PA's support for an instantaneous wide operation bandwidth.

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A CMOS Broadband Power Amplifier With a Transformer-Based High-Order Output Matching Network

A 2.45 GHz fully differential CMOS power amplifier (PA) with high efficiency and linearity is presented. For this work, a 0.18-/spl mu/m standard CMOS process with Cu-metal is employed and all components of the two-stage circuit except an output transformer and a few bond wires are integrated into one chip. To improve the linearity, an optimum gate bias is applied for the cancellation of the nonlinear harmonic generated by g/sub m3/ and a new harmonic termination technique at the common source node is adopted along with normal harmonic termination at the drain. The harmonic termination at the source effectively suppresses the second harmonic generated from the input and output. The amplifier delivers a 20.5dBm of P/sub 1dB/ with 17.5 dB of power gain and 37% of power-added efficiency (PAE). Linearity measurements from a two-tone test show that the power amplifier with the second harmonic termination improves the IMD3 and IMD5 over the amplifier without the harmonic termination by maximally 6 dB and 7 dB, respectively. Furthermore, the linearity improvements appear over a wide range of the power levels and the linearity is maintained under -45 dBc of IMD3 and -57dBc of IMD5 when the output power is backed off by more than 5dB from P/sub 1dB/. From the OFDM signal test, the second harmonic termination improves the error vector magnitude (EVM) by over 40% for an output power level satisfying the 4.6% EVM specification.

A highly linear and efficient differential CMOS power amplifier with harmonic control

A single-chip linear CMOS PA for OFDM WLAN applications adopts a fully differential topology with transformer-type output matching and operates from a 3.3V supply. All of the components, including the input balun and output transformer, are integrated on a single 0.18mum CMOS die and no off-chip component is required

A single-chip linear CMOS power amplifier for 2.4 GHz WLAN

To accurately understand the linear characteristics of a heterojunction bipolar transistor (HBT), we developed an analytical nonlinear HBT model using Volterra-series analysis. The model considers four nonlinear components: r/sub /spl pi//, C/sub diff/, C/sub depl/, and g/sub m/. It shows that nonlinearities of r/sub /spl pi// and C/sub diff/ are almost completely canceled by g/sub m/ nonlinearity at all frequencies. The residual g/sub m/ nonlinearity is highly degenerated by input circuit impedances. Therefore, r/sub /spl pi//, C/sub diff/, C/sub depl/, and g/sub m/ nonlinearities generate less harmonics than C/sub bc/ nonlinearity. If C/sub bc/ is linearized, g/sub m/ is the main nonlinear source of HBT, and C/sub depl/ becomes very important at a high frequency. The degeneration resistor R/sub E/ is more effective than R/sub B/ for reducing g/sub m/ nonlinearity. This analysis also shows the dependency of the third-order intermodulation (IM3) on the terminations of the source second harmonic impedances. The IM3 of HBT is significantly reduced by setting the second harmonic impedances of Z/sub S/,/sub 2/spl omega/2/ = 0 and Z/sub S/,/sub /spl omega/2-/spl omega/1/ = 0.

Analysis of nonlinear behavior of power HBTs

The linearity of a 0.18-/spl mu/m CMOS power amplifier (PA) is improved by adopting a deep n-well (DNW). To find the reason for the improvement, bias dependent nonlinear parameters of the test devices are extracted from a small-signal model and a Volterra series analysis for an optimized nMOS PA with a proper matching circuit is carried out. From the analysis, it is revealed that the DNW of the nMOS lowers the harmonic distortion generated from the intrinsic gate-source capacitance (C/sub gs/), which is the dominant nonlinear source, and partially from drain junction capacitance (C/sub jd/). Single-ended and differential PAs for 2.45-GHz WLAN are designed and fabricated using a 0.18-/spl mu/m standard CMOS process. The single-ended PA with the DNW improves IMD3 and IMD5 about 5 dB with identical power performances, i.e., 20 dBm of P/sub out/, 18.7 dB of power gain and 31% of power-added efficiency (PAE) at P/sub 1dB/. The IMD3 and IMD5 are below -40 dBc and -47dBc, respectively. The differential PA with the DNW also shows about 7 dB improvements of IMD3 and IMD5 with 20.2 dBm of P/sub out/, 18.9 dB of power gain and 35% of PAE at P/sub 1dB/. The IMD3 and IMD5 are below -45 dB and -57 dBc, respectively. These performances of the linear PAs are state-of-the-art results.

Highly linear 0.18-/spl mu/m CMOS power amplifier with deep n-Well structure

A 2.4-GHz Doherty CMOS power amplifier (PA) with ultra-high efficiency [power added efficiency (PAE)] is presented. A 0.13-mum standard CMOS process is employed and the two-stage circuit is configured for a 3.2-V operation. For a compact realization of the circuit, all matching circuits including a quarter wave transformer and input phase compensation transmission lines are implemented with lumped components. To modulate properly and maximize the PAE at P1 dB, the input power of the class C peaking power cell is adjusted by optimizing the gate bias of the peaking driver cell. By doing so, the gain compression of the carrier cell is compensated by the gain expansion of the peaking cell up to the full power. This amplifier delivers a 22.7dBm of P1 dB and 60% of PAE with 25dB of power gain at 2.4 GHz. The PAE at 5 dB backed-off power level shows about 35%. The excellent PAE of the circuit is the best data ever reported from linear CMOS PAs. The successful demonstration of the Doherty CMOS PA with lumped components is expected to be applied for a full-integration of the circuit

Jongchan Kang

Papers

A highly linear and efficient differential CMOS power amplifier with harmonic control

A single-chip linear CMOS power amplifier for 2.4 GHz WLAN

Analysis of nonlinear behavior of power HBTs

Highly linear 0.18-/spl mu/m CMOS power amplifier with deep n-Well structure

A Ultra-High PAE Doherty Amplifier Basedon 0.13- $mu$ m CMOS Process