Showing papers by "Jongwook Jeon published in 2023"

Well-Balanced Ambipolar Charge Transport of Diketopyrrolepyrrole-Based Copolymers: Organic Field-Effect Transistors and High-Voltage Logic Applications.

Abstract: A PDPADPP copolymer, composed of diketopyrrolopyrrole (DPP) and a cyano (nitrile) group with a vinylene spacer linking two benzene rings, was synthesized via a palladium-catalyzed Suzuki coupling reaction. The electrical performance of PDPADPP in organic field-effect transistors (OFETs) and circuits was investigated. The OFETs based on PDPADPP exhibited typical ambipolar transport characteristics, with the as-cast OFETs demonstrating low field-effect hole and electron mobility values of 0.016 and 0.004 cm2 V-1 s-1 , respectively. However, after thermal annealing at 240 °C, the OFETs exhibited improved transport characteristics with highly balanced ambipolar transport, showing average hole and electron mobility values of 0.065 and 0.116 cm2 V-1 s-1 , respectively. To verify the application of the PDPADPP OFETs in high-voltage logic circuits, compact modeling using the industry-standard small-signal Berkeley short-channel IGFET model (BSIM) was performed, and the logic application characteristics were evaluated. The circuit simulation results demonstrate excellent logic application performance of the PDPADPP-based ambipolar transistor and illustrate that the device annealed at 240 °C exhibits ideal circuit characteristics. This article is protected by copyright. All rights reserved.

Accurate Layout-Dependent Effect Model in 10nm-Class DRAM Process Using Area-Efficient Array Test Circuits

Abstract: This study presents an accurate model for non-monotonic layout-dependent effects (LDEs) measured using 10nm-class dynamic random access memory technology. To collect the LDE measurement data, a test module with an individually addressable array of 240 transistors has been developed. The proposed test module occupies a small area of 0.1 square millimeters with a density 15 times higher than that of typical scribe-line circuits. The proposed model employs a novel empirical function to precisely describe the non-monotonic dependence on each pair of geometrical parameters, such as the diffusion lengths, lateral/vertical spacings to the adjacent shallow trench isolations, and gate-to-contact distances. Additionally, this model can be easily realized as a sub-circuit model in standard circuit simulators, requiring only two additional tuning parameters for the core transistor. The fitted model demonstrates excellent agreement with the measured values obtained from test modules (802 transistors in total), achieving mean absolute errors of 0.7% for the drain current in the saturation region and 4.7 mV for the threshold voltage.

Non-volatile logic-in-memory ternary content addressable memory circuit with floating gate field effect transistor

Abstract: Due to the limitations of the currently widely used von Neumann architecture-based computing system, research on various devices and circuit systems suitable for logic-in-memory computing applications has been conducted. In this work, the silicon-based floating gate memory cell transistor structure, which has been attracting attention as a memory to replace the dynamic random access memory or NAND Flash technology, was newly recalled, and its applicability to logic-in-memory application was confirmed. This floating gate field effect transistor (FGFET) has the advantage that the compatibility of the existing silicon-based complementary metal–oxide–semiconductor (CMOS) process is far superior to that of logic-in-memory application devices to which materials with new memory characteristics are applied. At the 32 nm technology node, which is the front node to which the planar MOSFET structure is applied, an analysis environment that can simultaneously analyze the device and circuit of the FGFET was established. For a seamless connection between FGFET-based devices and circuit analysis, the compact model of the FGFET was developed, which is applied to logic-in-memory ternary content addressable memory (TCAM) circuit design. It was verified that the two types of logic-in-memory TCAM circuits to which FGFETs are applied are superior to a conventional CMOS FET-based TCAM circuit in the number of devices used (=circuit area) and power/energy efficiency.

Modulation of Contact Resistance of Dual-Gated MoS2 FETs Using Fermi-Level Pinning-Free Antimony Semi-Metal Contacts.

Abstract: Achieving low contact resistance (RC ) is one of the major challenges in producing 2D FETs for future CMOS technology applications. In this work, the electrical characteristics for semimetal (Sb) and normal metal (Ti) contacted MoS2 devices are systematically analyzed as a function of top and bottom gate-voltages (VTG and VBG ). The semimetal contacts not only significantly reduce RC but also induce a strong dependence of RC on VTG , in sharp contrast to Ti contacts that only modulate RC by varying VBG . The anomalous behavior is attributed to the strongly modulated pseudo-junction resistance (Rjun ) by VTG , resulting from weak Fermi level pinning (FLP) of Sb contacts. In contrast, the resistances under both metallic contacts remain unchanged by VTG as metal screens the electric field from the applied VTG . Technology computer aided design simulations further confirm the contribution of VTG to Rjun , which improves overall RC of Sb-contacted MoS2 devices. Consequently, the Sb contact has a distinctive merit in dual-gated (DG) device structure, as it greatly reduces RC and enables effective gate control by both VBG and VTG . The results offer new insight into the development of DG 2D FETs with enhanced contact properties realized by using semimetals.