This paper presents a precision CMOS temperature-to-digital converter (TDC), which senses the temperature-dependent base–emitter voltage of substrate PNPs. Measurements on 20 samples from one batch show that it achieves an inaccuracy of ±60 mK ( $3~\sigma $ ) from −55 °C to +125 °C, after a single room-temperature trim. This state-of-the-art result is mainly due to the extensive use of dynamic error cancellation techniques to generate the PNP’s collector currents, thus minimizing the spread in their base–emitter voltages, together with a digital PTAT trim to correct for the spread in the PNP’s saturation currents. The effect of process variation on the TDC’s inaccuracy was investigated by measuring 80 samples from three different batches. Using the same calibration parameters, they exhibit a maximum untrimmed inaccuracy of ±2 °C ( $3~\sigma $ ) from −55 °C to +125 °C. This drops to ±100 mK ( $3~\sigma $ ) after a single point trim. The proposed TDC thus reduces calibration costs by obviating the need for batch-specific calibration parameters, which would otherwise require the multipoint calibration of several samples. The effect of the PNP’s current gain $\beta $ was also investigated with the help of a novel $\beta $ -detection circuit. Implemented in 0.16-μm CMOS, the TDC occupies 0.16 mm2 and draws 4.6 $\mu \text{A}$ from 1.5 to 2 V supply voltages. It achieves a resolution Figure of Merit of 7.8 pJ°C2, and a state-of-the-art supply sensitivity of 0.01 °C/V.

/pdf/a-bjt-based-temperature-to-digital-converter-with-60-mk-3-3wkzloeu93.pdf

A BJT-Based Temperature-to-Digital Converter With ±60 mK ( $3~\sigma$ ) Inaccuracy From −55 °C to +125 °C in 0.16-μm CMOS

This paper describes the design of a precision bipolar junction transistor based temperature sensor implemented in standard 0.7- μ m CMOS technology. It employs substrate p-n-ps as sensing elements, which makes it insensitive to the effects of mechanical (packaging) stress and facilitates the use of low-cost packaging technologies. The sensor outputs a duty-cycle-modulated signal, which can easily be interfaced to the digital world and, after low-pass filtering, to the analog world. In order to eliminate the errors caused by the component mismatch, chopping and dynamic element matching (DEM) techniques have been applied. The required component shuffling was done concurrently rather than sequentially, resulting in a fast DEM scheme that saves energy without degrading accuracy. After a single-temperature trim, the sensor's inaccuracy is ±0.1 °C (−20 to 60 °C) and ±0.3 °C (−45 to 130 °C), respectively. Measurements of sensors in different packages show that the package-induced shift is less than 0.1 °C. Measurements of eight sensors over 367 days show that their output drift is less than 6 mK. While dissipating only 200 μ W, the sensor achieves a resolution of 3 mK (rms) in a 1.8-ms measurement time, and a state-of-the-art resolution figure of merit of 3.2 pJK2. This combination of high accuracy, high resolution, high speed, and low-energy consumption makes this sensor suited for commercial and industrial applications.

/pdf/an-accurate-bjt-based-cmos-temperature-sensor-with-duty-27zeu8ke7p.pdf

An Accurate BJT-Based CMOS Temperature Sensor With Duty-Cycle-Modulated Output

Test time and test complexity reduction has become a critical challenge in modern RF testing. Prior “alternative” test methods have achieved fast testing at the cost of using supervised learning algorithms that require “training”. In contrast, behavioral model parameter estimation based test methods require the use of accurate models but no “training” is necessary, reducing test deployment costs. In this work, a new test generation approach is proposed that allows behavioral model parameter estimation to be performed from a single optimized OFDM data frame. A genetic multi-tone test stimulus optimization algorithm is developed to maximize the accuracy with which a nonlinear solver can determine RF transceiver model parameters from raw downconverted test response data. The transceiver model proposed is the most comprehensive to date and includes AM-PM distortion and 5th order nonlinearity effects. Simulation results show that using the optimized multitone test stimulus, all the model parameters can be computed accurately using a single data acquisition (4X-5X faster than prior parameter estimation techniques and comparable to alternative test times). Data from an experiment performed on a hardware prototype validates the proposed concept.

Optimized Multitone Test Stimulus Driven Diagnosis of RF Transceivers Using Model Parameter Estimation

Thermal sensing is a key power management feature in microprocessor products and other integrated circuits. There can be as many as 40 sensors on a chip. Thus, it is important for these sensors to have a highly compact area, as well as low energy. In this paper, we report a novel resistor-based thermal sensor with an area of 0.01 mm2 in 65-nm process, an energy consumption of 0.9 nJ/conversion, and a conversion speed of 80 $\mu \text{s}$ . This sensor is one of the smallest, fastest, and lowest energy sensors reported which utilize resistors as the sensing element, making it optimal for CPU applications. The sensor has a competitive resolution figure of merit of 0.02 nJ $\cdot \text {K}^{2}$ , as well as a relative inaccuracy of 1.4 °C, which easily meets the accuracy requirements of these applications. The circuit architecture is based on the measurement of an RC time constant using a novel amplifier/comparator circuit, along with a dynamic bias for power savings.

Miniaturized, 0.01 mm 2 , Resistor-Based Thermal Sensor With an Energy Consumption of 0.9 nJ and a Conversion Time of 80 $\mu$ s for Processor Applications

A dual-mode digital power gate (PG) and linear low-drop-out regulator (LDO) has been demonstrated in 14 nm. A modified flipped source follower driver circuit is used to minimize dI / dt droops. The LDO has a novel compensation method which utilizes capacitance multiplication and can drive a 1–7 $\upmu\text{F}$ load without any external compensation elements. This LDO exhibits high-current drive capability (3 A) at low-dropout voltages ( $ ) and high-current efficiency ( $> {99}\%$ ), making it suitable to drive a microprocessor core.

Dual-Mode Low-Drop-Out Regulator/Power Gate With Linear and On–Off Conduction for Microprocessor Core On-Die Supply Voltages in 14 nm

Pseudorandom test of analog and mixed-signal circuits provides a low-cost test solution; however, its application has been restricted to linear circuit testing. This paper presents an efficient pseudorandom test method for nonlinear circuits. The method uses a simplified Volterra series model to characterize nonlinear behaviors of devices under test (DUTs) accurately with a low complexity algorithm. A multilevel pseudorandom sequence is used to excite DUTs over a wide range of frequencies and generate a spread-spectrum output response. The cross spectral density of the input test pattern and output response is computed to estimate the parameters of Volterra series and predict the performance of DUTs. In addition, the method can be used to compensate nonlinear errors of DUTs and improve performance. The mathematical background and simulation results are presented to validate the proposed method

Pseudorandom Test for Nonlinear Circuits Based on a Simplified Volterra Series Model

A temperature sensor uses a semiconductor device that has a known voltage drop characteristic that is proportional to absolute temperature (PTAT). A controllable current source is coupled to the semiconductor device and is operable to sequentially inject a bias current having a value I(bias) and fixed ratio N of I(bias) into the semiconductor device. A delta sigma analog to digital converter (ADC) has an input coupled to the semiconductor device. The delta sigma ADC is configured to sample and integrate a sequence of voltages pairs produced across the semiconductor device by repeatedly injecting an ordered sequence of selected bias currents into the semiconductor device. The ordered sequence of selected bias currents comprises M repetitions of (N×I(bias); I(bias)) and one repetition of (M×I(bias); M×N×I(bias)).

Resistance and offset cancellation in a remote-junction temperature sensor

A phase-locked loop (PLL) includes a state machine programmed to automatically produce a set of control signals to select a charge-pump current and integrating capacitance value to automatically adjust a loop bandwidth of the PLL. A charge-pump DAC generates a charge-pump current of magnitude controlled by the state machine control signals. An integrator integrates the charge-pump output current to produce an integrated charge-pump output signal. The integrator has a plurality of capacitors switchably selected by control signals from the state machine to produce an integrating capacitance value. A voltage controlled oscillator (VCO) produces a PLL output frequency in response to the integrated charge-pump output signal.

Autoconfigurable phase-locked loop which automatically maintains a constant damping factor and adjusts the loop bandwidth to a constant ratio of the reference frequency

An embedded remote junction temperature sensor (RTS) with an inaccuracy of $0.4^{\circ}$ C $(3\sigma)$ for temperature range from $-$ 40 $^{\circ}$ C to 130 $^{\circ}$ C is presented. Using a digital beta compensation technique, series resistance cancellation and global offset and noise coupling cancellation, the sensor is capable of handling a variety of remote BJTs which are either directly mounted on a PCB or embedded in SoCs. It can accommodate a series resistance of more than 500 $\Omega$ and beta values down to around 1.5. The RTS has been integrated with a microcontroller core implemented in a 65 nm digital CMOS process. It shares an external reference voltage source with other data converters on the SoC. Measured results from a set of 16 samples and four BJTs are presented.

An Embedded 65 nm CMOS Remote Temperature Sensor With Digital Beta Correction and Series Resistance Cancellation Achieving an Inaccuracy of 0.4 $^{\circ}$ C (3 $\sigma$ ) From $-$ 40 $^{\circ}$ C to 130 $^{\circ}$ C

With the increasing pressure to obtain near-zero defect rates for the automotive industry, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, DC-DC converters, and data converters. This paper presents an extremely low-cost built-in self-test technique for PLLs specifically designed for fault detection. The methodology relies on exciting the PLL loop in one location via a pseudo-random signal with noise characteristics and observing the response from another location in the loop via all digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with a PLL under test is designed in 65nm technology. Fault simulations performed at the transistor and system level show that majority of non-catastrophic faults that result in parametric failures can be detected with the proposed approach.

Joonsung Park

Papers

Pseudorandom Test for Nonlinear Circuits Based on a Simplified Volterra Series Model

Resistance and offset cancellation in a remote-junction temperature sensor

Autoconfigurable phase-locked loop which automatically maintains a constant damping factor and adjusts the loop bandwidth to a constant ratio of the reference frequency

An Embedded 65 nm CMOS Remote Temperature Sensor With Digital Beta Correction and Series Resistance Cancellation Achieving an Inaccuracy of 0.4 $^{\circ}$ C (3 $\sigma$ ) From $-$ 40 $^{\circ}$ C to 130 $^{\circ}$ C

Digital Built-in Self-Test for Phased Locked Loops to Enable Fault Detection