コンピュータ・サイエンス : ACM computing surveys

The use of static random access memory (SRAM)-based field programmable gate arrays (FPGAs) in harsh radiation environments has grown in recent years. These types of programmable devices require special mitigation techniques targeting the configuration memory, the user logic, and the embedded RAM blocks. This article provides a comprehensive survey of the literature published in this rich research field during the past 10 years. Furthermore, it can also serve as a tutorial for space engineers, scientists, and decision makers who need an introduction to this topic.

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Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

Vision-based navigation has become increasingly important in a variety of space applications for enhancing autonomy and dependability. Future missions, such as active debris removal for remediating...

https://arc.aiaa.org/doi/pdf/10.2514/1.I010555

High-Performance Embedded Computing in Space: Evaluation of Platforms for Vision-Based Navigation

Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

Field Programmable Gate Array Applications—A Scientometric Review

Reconfigurable hardware is gaining a steadily growing interest in the domain of space applications. The ability to reconfigure the information processing infrastructure at runtime together with the high computational power of today's FPGA architectures at relatively low power makes these devices interesting candidates for data processing in space applications. Partial dynamic reconfiguration of FPGAs enables maximum flexibility and can be utilized for performance optimization, for improving energy efficiency, and for enhanced fault tolerance. To be able to prove the effectiveness of these novel approaches for satellite payload processing, a highly scalable prototyping environment has been developed, combining dynamically reconfigurable FPGAs with the required interfaces such as SpaceWire, MIL-STD-1553B, and SpaceFibre. The developed systems have been enabled to space harsh environments thanks to an analytical analysis of the radiation effects on its most critical reconfigurable components. Aiming at that scope, a new algorithm for the analysis of critical radiation effects, in particular, related to Single Event Upsets (SEUs) and Multiple Event Upsets (MEUs) has been developed to obtain an effective estimation of the radiation impact and enabling the tuning of the component mapping reducing the routing interaction between the reconfigurable placed modules in their different feasible positions. The experimental performance of the system has been evaluated by a proper dynamic reconfiguration scenario, demonstrating a partial reconfiguration at 400 MByte/s, blind and readback scrubbing is supported and the scrub rate can be adapted individually for different parts of the design. The fault tolerance capability has been proven by means of a new analysis algorithm and by fault injection campaigns of SEUs and MCUs into the FPGA configuration memory.

A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing

This paper presents a novel methodology that allows a systematic availability analysis of satellite payload data processing systems implemented on static random-access memory-based field-programmable gate arrays. The methodology allows 1) comparison of different fault detection, isolation, and recovery schemes and 2) prediction of the expected system availability in a particular radiation environment. Furthermore, it advances the state of the art by analyzing embedded block RAMs and employing a novel fault injection algorithm that enables more complex stochastic models. The applicability of the method is demonstrated by a case study representing a high-availability payload data processing application. Since block RAMs are also taken into account, the availability prediction precision is greatly increased. It is shown that the reliability prediction for two border cases in which the block RAMs are either ignored or assumed to be fully susceptible can differ as much as 75%.With the proposed block RAM profiling tool, it is possible to determine a realistic reliability figure that is eventually required for the accurate estimation of the system availability.

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Availability analysis for satellite data processing systems based on SRAM FPGAs

Embedded devices used in the space industry have to face stringent requirements imposed by their deployment environment, namely high reliability, limited resources, and challenges in heat dissipation. In addition, to make matters worse, the demand for advanced processing capability is growing steadily to meet future exploration and deep space mission requirements. At the European Space Agency, ongoing studies are focusing the use of reconfigurable and adaptable systems to help finding solutions to the aforementioned issues as well as to how reconfigurable systems can aid in mission cost reductions. After giving a general overview of the efforts spent in this direction, this paper presents two concrete examples of on going research activities funded by the European Space Agency.

The future of embedded systems at ESA: Towards adaptability and reconfigurability

Instruments on spacecrafts or even complete payload data handling units are typically controlled by a dedicated data processing unit. This data processing unit exercises control of subsystems and telecommand processing as well as processing of acquired science data. With increasing detector resolutions and measurement speeds the processing demands are rising rapidly. To fulfill these increasing demands under the constraints of limited power budgets, a dedicated hardware design as a System on Chip (SoC), e.g. in a FPGA, has been shown to be a viable solution. In previous papers [1], [2] we have presented our Network on Chip (NoC) solution SoCWire as a higly efficient and reliable approach for a dynamic reconfigurable architectures. However, the control task still requires a sequential processor which is able to execute software. The LEON processor is a processor that is available in a fault tolerant version suitable for space applications and is accessible as an open source design. This paper presents an efficient solution for a combined NoC and classic processor bus-based communication architecture, i.e. the AHB2SOCW bridge as an efficient connection between a SoCWire network and a LEON processor bus systems. Direct memory access enables the AHB2SOCW bridge to operate efficiently. The resource utilization and obtainable data rates are presented as well as an outlook for the intended target application, which is an efficient SoC controller for a reconfigurable processing platform based on FPGAs.

AMBA to SoCWire network on Chip bridge as a backbone for a Dynamic Reconfigurable Processing unit

In this paper, a Fault Detection, Isolation and Recovery approach to SRAM-based FPGAs in payload data processing applications on-board spacecraft is presented. The approach is able to support different reliability requirements through on-line configuration of the target system adapting it to new constraints in terms of reliability and power consumption. The core of the approach is a novel Distributed Failure Detection technique, aimed at Network-on-Chip implementations, which embeds failure detection mechanisms into the routing switches of the network.

Jorgen Ilstad

Papers

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

Availability analysis for satellite data processing systems based on SRAM FPGAs

The future of embedded systems at ESA: Towards adaptability and reconfigurability

AMBA to SoCWire network on Chip bridge as a backbone for a Dynamic Reconfigurable Processing unit

Adaptive FDIR framework for payload data processing systems using reconfigurable FPGAs