Showing papers by "José Monteiro published in 1998"

Finite state machine decomposition for low power

Abstract: Clock-gating techniques have been shown to be very effective in the reduction of the switching activity in sequential logic circuits The authors describe a new clock-gating technique based on finite state machine (FSM) decomposition They compute two sub-FSMs that together have the same functionality as the original FSM For all the transitions within one sub-FSM, the clock for the other sub-FSM is disabled To minimize the average switching activity, they search for a small cluster of states with high stationary state probability and use it to create the small sub-FSM This way one will have a small amount of logic that is active most of the time, during which is disabling a much larger circuit, the other sub-FSM They provide a set of experimental results that show that power consumption can be substantially reduced, in some cases up to 80%

Sequential logic optimization for low power using input-disabling precomputation architectures

Abstract: Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a logic circuit, thereby reducing switching activity and power dissipation, without changing logic functionality. In sequential precomputation, output values required in a particular clock cycle are selectively precomputed one clock cycle earlier, and the original logic circuit is "turned off" in the succeeding clock cycle. We target a general precomputation architecture for sequential logic circuits, and show that it is significantly more powerful than the architecture previously treated in the literature. The very power of this architecture makes the synthesis of precomputation logic a challenging problem. We present a method to automatically synthesize precomputation logic for this architecture. Up to 66% reduction in power dissipation is possible using the proposed architecture. For many examples, the proposed architecture result in significantly less power dissipation than previously developed methods.

Exploiting Don't Car es in Test Patterns to Reduce Power During BIST

Abstract: For a significant number of electronic systems used in safety-critical applications circuit testing is performed periodically. For these systems, power dissipation due to BuiltIn Self Test (BIST) can represent a significant percentage of the overall power dissipation. One possible solution to address this problem consists of test pattern reordering with the purpose of reducing the amount of power dissipated during circuit testing. By reordering test patterns one is able to find test sequences for which power dissipation is minimized. Moreover, a key observation is that test patterns are in general expected to exhibit don’t cares, which can naturally be exploited during test pattern reordering. In this paper we describe efficient algorithms for test pattern reordering in the presence of don’ t cares. Preliminary experimental results amply confirm that the power savings due to test pattern reordering using don’ t cares can be significant.

Power optimization of combinational modules using self-timed precomputation

Abstract: Precomputation has recently been proposed as a very effective power management technique. Precomputation works by preventing some of the inputs from being loaded into the input registers, thus significantly reducing the switching activity in the circuit. In this paper we present a self-timed approach for the precomputation of combinational logic circuits. This technique allows for maximum power savings without the need of a clock signal. However we may incur in some delay penalty. We describe how to achieve significant power reductions without increasing the maximum delay, by choosing a judicious placement of the latches in the combinational logic circuit. Experimental results are presented for arithmetic modules, confirming that power dissipation can be greatly reduced with marginal increases in circuit area and almost zero delay increase.

Techniques for power management at the logic level

Abstract: Power dissipation has recently emerged as one the most critical design constraints. A wide range of techniques has already been proposed for the optimization of logic circuits for low power. Power management methods are among the most effective techniques for power reduction. These methods detect periods of time during which parts of the circuit are not doing useful work and shut them down by either turning off the power supply or the clock signal. In this paper, some of the most representative logic-level power management techniques that have recently been proposed are reviewed. Each method uses a different approach to identify the input conditions for which the circuit (or part of) can be disabled. These techniques are put into perspective and recent results are discussed.

Power Estimation Under User-Specified Input Sequences and Programs

Abstract: We describe an approach to estimate the average power dissipation in sequential logic circuits under user-specified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the estimation of the power dissipated when the controller or processor is running specific application programs. Current approaches to sequential circuit power estimation are limited by the fact that the input sequences to the sequential circuit are assumed to be uncorrelated. In reality, the inputs come from other sequential circuits, or are application programs. In this paper we show how user-specified sequences and programs can be modeled using a finite state machine, termed an input-modeling finite state machines or IMFSM. Power estimation can be carried out using existing sequential circuit power estimation methods on a cascade circuit consisting of the IMFSM and the original sequential circuit.