Showing papers by "Jose Silva-Martinez published in 2021"
TL;DR: The design issues and advantages of analog linear low-dropout regulators are discussed in this article, where the authors revises the recent design trends of linear low dropout regulators and revisited all three architectures.
Abstract: This brief revises the recent design trends of linear low-dropout regulators. The design issues and advantages of analog LDOs (ALDO) are discussed. High-performance operation and high rejection to supply noise when delivering large current values is a major advantage of the ALDO, but transient response when transitioning from standby operation to full load is a major issue; the main limitation is the slow charging/discharging of the large gate’s capacitor of the pass transistor. This issue is more critical when designing full-on chip ALDOs, where large load capacitors are not available. Digital LDOs (DLDO) employ digital controllers that drive the segmented pass transistor, in most of the cases operate in triode region. The digital nature of the DLDO scales with the technology, but its rejection to supply noise is limited. Mixed-mode LDOs take advantage of the properties of both ALDO and DLDOs. Transient is managed by the agile DLDO and steady state operation is mainly handled by the clock glitch free ALDO. In this brief, all three architectures are revisited.
13 citations
07 Jun 2021
TL;DR: In this paper, a 2.3-3.9 GHz fractional-N phase locked loop (PLL) with charge pump and a time-to-digital converter (TDC) based calibration for reference and fractional spurs reduction suitable for frequency synthesizers used in 5G mobile communication systems is introduced.
Abstract: A 2.3-3.9 GHz fractional-N phase locked loop (PLL) with charge pump and a time-to-digital converter (TDC) based calibration for reference and fractional spurs reduction suitable for frequency synthesizers used in 5G mobile communication systems is introduced in this paper. The charge pump PLL includes a digital phase processor composed by a TDC, digital filters and a DTC and it is used for monitoring, tracking, and filtering both reference and fractional spurs simultaneously. Calibrated sub-ranging TDCs and DTC with 1 ps resolution are employed. A non-invasive master-slave calibration methodology is applied to TDCs and DTC with Vernier delay line structure to achieve the required INL and DNL performances. Fabricated in a mainstream 40-nm technology, the PLL is characterized, showing a reference spur level of −108.3 dBc and a fractional spur under −95.0 dBc. The frequency synthesizer's total power consumption when operating at 3.3 GHz is 15.7 mW.
2 citations
Patent•
02 Mar 2021
TL;DR: In this paper, a segmented PA with two-path timing mismatch calibration is proposed to improve ACLR performance over different signal transitions, process, voltage and temperature (PVT) variations and device aging.
Abstract: An apparatus and methods for timing mismatch in a power amplifier includes a segmented PA with two-path timing mismatch calibration to improve ACLR performance over different signal transitions, process, voltage and temperature (PVT) variations and device aging; a fast and efficient algorithm for measuring and calibrating the delay of two paths (signal path and control path); a signal magnitude variation detection circuit, such as flash ADC, with improved comparator's performance for RF signal processing and minimum delay. A method for choosing the threshold voltage of the magnitude variation detection circuit, according to status of the signals and orthogonal frequency-division multiplexing (OFDM) related standards; other critical blocks.