Juan Gómez Luna

TL;DR: In this paper, a cross-layer design is proposed to expose set operations using a novel programming paradigm, express and execute these operations efficiently with carefully designed set-centric ISA extensions called SISA, and use PIM to accelerate SISA instructions.

TL;DR: In this article, the authors propose a hardware-software cooperative mechanism that enables highly efficient indexing and storage of sparse matrices by explicitly enabling the hardware to recognize and exploit sparsity in data.

TL;DR: This paper proposes SMASH, a hardware-software cooperative mechanism that enables highly-efficient indexing and storage of sparse matrices and devise a novel software encoding based on a hierarchy of bitmaps that can be used to efficiently compress any sparse matrix, regardless of the extent and structure of sparsity.

TL;DR: A new substrate, FIGARO, is proposed that uses existing shared global buffers among subarrays within a DRAM bank to provide support for in-DRAM data relocation across subar-rays at the granularity of a single cache block, and it is shown that FIGCache outperforms state-of-the-art in- DRAM caching techniques, and that its performance gains are robust across many system and mechanism parameters.

TL;DR: In this paper, a fine-grained in-DRAM cache called FIGCache is proposed to cache only frequently-accessed portions of different DRAM rows in a designated region of DRAM.