Standard-cell design and characterization are presented for 7-nm CMOS platform technology targeting low-power and high-performance applications with the tightest contacted poly pitch of 42 nm and a metallization pitch of 32 nm in the FinFET technology. Two standard-cell architectures for 7 nm, a 9-track library and a 7.5-track library have been designed, introducing an extra middle-of-line layer to enable an efficient layout of the 7.5-track cells. The 7.5-track cells are on average smaller than the 9-track cells. With the strict design constraints imposed by self-aligned quadruple patterning and self-aligned double patterning, careful design and technology co-optimization is performed.

Architectural strategies in standard-cell design for the 7 nm and beyond technology node

Line-edge roughness induced fin-edge roughness (FER) is the primary source of $V_{T}$ variation in FinFETs. Conventionally, stochastic simulations are performed to predict the device variability due to FER for a technology, which are computationally expensive. An analytical formulation to predict variability due to FER enables understanding of the effect of input parameters as well as provides quantitative results at fractional computational costs. In this paper, we develop and present an analytical model to estimate saturation $V_{T}$ ( $V_{{T\rm {-sat}}})$ variability due to FER. The model is capable of capturing the $V_{T}$ variability dependence on device parameters ( $L_{G}$ and $W_{\mathrm{ fin}}$ ) and variability parameters (correlation length $\Lambda $ and standard deviation $\Delta )$ accurately. The entire $V_{{T\rm {-sat}}}$ distribution obtained by the model is also presented and compared against the $V_{{T\rm {-sat}}}$ distribution of stochastic simulations to show that the model captures the distribution effectively. We show that not only $\sigma V_{T}$ but even $\mu V_{T}$ is affected by variability parameters. Hence, such modeling is critical to defining nominal FinFET structure ( $L_{G}$ and $W_{\mathrm{ fin}}$ ), which is affected by variability ( $\Lambda $ and $\Delta $ ) especially for scaled FinFETs, where quantum-confinement effects are enhanced.

An Analytical Model to Estimate FinFET’s $V_{T}$ Distribution Due to Fin-Edge Roughness

A generalized edge-placement yield model for the cut-hole patterning process is developed. It incorporates the cut-hole
overlay errors, cut-hole and grating line/space CD variations into a unified physical model to investigate the key
parameters that affect the edge-placement yield. The yield related features are identified first and probability-of-failure
(POF) functions are introduced to construct the yield formula. The variable number in the yield integral is reduced from
four to two by a special transformation method. Our calculation results show that the cut-hole overhang and (grating)
line/space CD must be optimized in order to achieve the maximum yield. The sensitivity of edge-placement yield to
various statistical parameters is investigated and the overlay errors are found to play a dominant role. We also study the
scaling trend of the edge-placement yield and show that non-trivial challenges of manufacturing (half-pitch) 7-nm
FinFET devices will require significantly improved overlay accuracy and process control.

A Generalized Edge-Placement Yield Model for the Cut-Hole Patterning Process

Line edge roughness (LER) is a critical variability source in scaled FinFETs. LER produces line width roughness (LWR) that causes threshold voltage ( ${V}_{T}$ ) variability. Various lithography techniques demonstrate characteristic LER-LWR relationship. For translating LER/LWR to the ${V}_{T}$ distribution, an analytical model for uncorrelated fin edges (correlation coefficient, $\rho ={0}$ ) has been presented in the literature. However, a range of correlation coefficients ( ${0}\le \rho \le {0.85}$ ) between two fin edges is experimentally observed for various lithography techniques. In this paper, we present an analytical model to predict $\rho $ dependent ${V}_{T}$ distribution for partially correlated fin edges in FinFETs. First, an analytical model of mean ( $\mu $ ) and standard deviation ( $\sigma $ ) for $\rho $ dependent minimum, maximum, and average fin width is presented. This is used to construct an equivalent simplified trapezoidal fin distribution. Second, percolation theory-based model is used to compute ${V}_{T}$ distribution from the fin distribution. The model is validated against well-calibrated TCAD simulations for a wide range of geometrical (channel length ${L}_{G}$ and nominal fin width ${W}_{\text {fin}})$ and LER variability (correlation length $\Lambda $ and correlation coefficient $\rho $ ) parameters to show excellent match. The model is 1000 times faster compared with TCAD simulations.

An Analytical Model to Estimate ${V}_{T}$ Distribution of Partially Correlated Fin Edges in FinFETs Due to Fin-Edge Roughness

In this work, the DC characteristic variability of 14-nm-gate HKMG trapezoidal bulk FinFET induced by different line edge roughness (LER) is for the first time studied by using experimentally validated 3D device simulation. By considering a time-domain Gaussian noise function, we compare four types of LER: Fin-LER inclusive of resist-LER and spacer-LER, sidewall-LER, and gate-LER for the trapezoidal bulk FinFET with respect to different fin angles. The resist-LER and sidewall-LER have large impact on characteristics fluctuation. For each type of LER, the V th fluctuation is comparable among fin angles.

The impact of fin/sidewall/gate line edge roughness on trapezoidal bulk FinFET devices

Self-aligned multiple patterning (SAMP) is a promising technology to scale IC devices to 7-nm half pitch and several 3- mask negative-tone SAMP processes for 2-D BEOL patterning applications have been proposed recently. In this paper, the existing coloring rules in self-aligned quadruple and sextuple patterning (SAQP and SASP) processes are reexamined first. We further discuss the geometric relation between various features and remove the unnecessary constraints, and develop improved layout decomposition algorithms for both processes. The cut-mask related overlay issue is addressed by proposing an edge-expansion solution when generating the cut patterns. Finally, we show that numerous standard M1 cells in the Open Cell Library, when slightly modified, can be successfully decomposed. This verifies the functionality of the new decomposition algorithms for continuous logic scaling to deep nano-scale using SAMP techniques.

A layout decomposition algorithm for self-aligned multiple patterning

In this paper, a generalized model to predict fin-width roughness (FWR) induced FinFET device variability is developed using the boundary perturbation method. An analytic solution to Poisson’s equation with a perturbed boundary is derived to describe the FWR effects on the sub-threshold electric potential and drain current. High model accuracy under various device operating conditions is demonstrated by a detailed comparison with TCAD simulations. The correlation among the threshold-voltage shift, dominant fin-roughness frequency, and phase difference (between two dominant fin-edge roughness functions) is identified. It is found that a periodic fluctuation of the threshold voltage can be induced by the phase difference, while more significant variations are observed at lower frequencies. Our study also shows that thinner gate oxide and wider fins will help to reduce the FWR effects.

A generalized model to predict fin-width roughness induced FinFET device variability using the boundary perturbation method

Correlating FinFET device variability to the spatial fluctuation of fin width

In this paper, we present a benchmarking study of directed self-assembly (DSA) and self-aligned multiple patterning (SAMP) techniques for potential applications in manufacturing 10-nm (half-pitch) IC devices. Using the self-aligned quadruple patterning (SAQP) process as an example, we compare their process characteristics and complexity/costs, identify the integration challenges, and propose various patterning solutions for both BEOL and FEOL applications. 
Major differences in DSA and SAQP mask strategy, layout decomposition algorithm, and pattern-generation modeling are discussed, and critical requirements of overlay accuracy and CD control for implementing a DSA process in NAND wordline patterning are indentified. DSA technique is found to be a complementary solution for certain niche applications and we suggest that our industry should allocate more R and D resources to solve the 2-D SAMP layout decomposition challenges for logic BEOL patterning. We also propose an “out-of-the-box” idea of combining DSA and SADP process to significantly improve the 2-D design flexibility and develop a layout decomposition algorithm for this hybrid process

Jun You

Papers

A layout decomposition algorithm for self-aligned multiple patterning

A generalized model to predict fin-width roughness induced FinFET device variability using the boundary perturbation method

Correlating FinFET device variability to the spatial fluctuation of fin width

Benchmarking process integration and layout decomposition of directed self-assembly and self-aligned multiple patterning techniques