/pdf/micro-total-analysis-systems-1-introduction-theory-and-27f7corp18.pdf

Micro Total Analysis Systems. 1. Introduction, Theory, and Technology

A lithographic apparatus configured to project a patterned beam of radiation onto a target portion of a substrate is disclosed. The apparatus includes a first radiation dose detector and a second radiation dose detector, each detector comprising a secondary electron emission surface configured to receive a radiation flux and to emit secondary electrons due to the receipt of the radiation flux, the first radiation dose detector located upstream with respect to the second radiation dose detector viewed with respect to a direction of radiation transmission, and a meter, connected to each detector, to detect a current or voltage resulting from the secondary electron emission from the respective electron emission surface.

Lithographic apparatus, and device manufacturing method

A high resolution and high data rate spot grid array printer system is provided, wherein an image is formed by scanning spot-grid array of optical beams across a substrate layered with a resist. High resolution is achieved by apodizing the optical beams to provide a narrower main lobe. Unwanted recordation of side lobes upon the substrate is prevented by assuring that the side lobes do not include energy above the threshold of the resist, using a memoryless resist, and by using a slanted and interleaved scan pattern adapted for use with the spot-grid array pattern and the memoryless characteristic of the resist.

Optical spot grid array printer

A maskless, extreme ultraviolet (EUV) lithography system uses microlens arrays to focus EUV radiation (at an operating wavelength of 11.3 nm) onto diffraction-limited (58-nm FWHM) focused spots on a wafer printing surface. The focus spots are intensity-modulated by means of microshutter modulators and are raster-scanned across a wafer surface to create a digitally synthesized exposure image. The system uses a two-stage microlens configuration to achieve both a high fill factor and acceptable transmission efficiency. EUV illumination is supplied by a 6 kHz xenon plasma source, and the illumination optics comprise an aspheric condenser mirror, a spherical collimating mirror, and two sets of flat, terraced fold mirrors that partition the illumination into separate illumination fields covering individual microlens arrays. (The system has no projection optics, because the image modulator elements are integrated with the microlens arrays.) The printing throughput is estimated to be 62 (300-mm) wafers per hour (assuming a resist exposure threshold of 20 mJ/cm 2 ), and print resolution is estimated at 70 nanometers for mixed positive- and negative-tone patterns (at k 1 =0.6).

Maskless, microlens EUV lithography system

In this paper, we survey key design for manufacturing issues for extreme scaling with emerging nanolithography technologies, including double/multiple patterning lithography, extreme ultraviolet lithography, and electron-beam lithography. These nanolithography and nanopatterning technologies have different manufacturing processes and their unique challenges to very large scale integration (VLSI) physical design, mask synthesis, and so on. It is essential to have close VLSI design and underlying process technology co-optimization to achieve high product quality (power/performance, etc.) and yield while making future scaling cost-effective and worthwhile. Recent results and examples will be discussed to show the enablement and effectiveness of such design and process integration, including lithography model/analysis, mask synthesis, and lithography friendly physical design.

Design for Manufacturing With Emerging Nanolithography

Masks have been identified as the high risk, high cost issue for extreme ultraviolet (EUV) lithography. Challenges in EUV mask technology such as providing a pellicle and correcting defects have prompted the search for a maskless technique. Here we describe two approaches in which the mask of a current EUV system is replaced by an array of micron-sized mirrors. Patterns are achieved by modulating individual mirrors to create selected bright and dark spots. In one approach, individual mirrors can be lowered by λ/4 to yield locally dark regions because of destructive interference. In another approach, each mirror is mounted on a cantilever. Selected cantilevers can be tilted such that incident light from those mirrors is out of the pupil of the imaging objective. The wafer is mechanically scanned and the object is electronically scrolled across the array of mirrors in order to build up the required pattern. We have simulated the mechanical properties of the micron-sized mirrors and some aerial images showin...

Maskless extreme ultraviolet lithography

Spacer based self-aligned multiple patterning (SAMP) techniques potentially allow us to scale integrated circuits down
to sub-10nm half pitch with no need of EUV lithography. In this paper, we shall present a general analysis of
technological merits, process complexity and costs of various SAMP techniques. It is shown that some SAMP
techniques such as self-aligned quadruple/sextuple patterning (SAQP/SASP) are more capable of increasing the pattern
density, while self-aligned triple patterning (SATP) is more beneficial to reducing process complexity by allowing
quasi-2D IC design and requiring fewer masks. Besides their different scaling/resolution capability and process
challenges, each SAMP technique is accompanied with unique characteristics of CD uniformity (CDU) and line-width
roughness (LWR), which indicates their application areas and the related IC design/fabrication methodologies vary
significantly by industry segment. Process costs of various self-aligned multiple patterning schemes are calculated,
which show that within the common resolution capability, SATP technique is the most cost effective while the
EUV+SADP approach only offers limited benefits.

Technological Merits, Process Complexity, and Cost Analysis of Self-aligned Multiple Patterning

A micromirror array for extreme ultraviolet (EUV) maskless lithography was designed and fabricated. The arrays are composed of devices with less than a 350 nm actuation gap and a surface area ranging from 1 μm2 to 20 μm2. The mirror layer is composed of silicon in lieu of the Mo/Si stack used for EUV mirrors in order to debug the process and to simplify the initial fabrication. Germanium was used as a sacrificial material while α-Si acts as a hinge for this parallel-plate design. Silicon migration into germanium was observed, so the thermal budget was restrained to 450 °C for the entire process. Scanning electron microscope images of working devices are provided.

Fabrication of parallel-plate nanomirror arrays for extreme ultraviolet maskless lithography

Disclosed is an actuator for a phase mirror array including a) a first support member extending perpendicularly from a surface of a mirror, b) a plurality of flexures engaging the first support member with the flexures being generally parallel to the surface of the mirror, c) second and third support members engaging opposing ends of the flexures, at least one of the second and third support members functioning as a first electrode, and d) a second electrode positioned in spaced parallel relationship with the flexures, whereby a voltage impressed across the first electrode and the second electrode causes displacement of the supported mirror on the support structure. The second electrode and one of the flexures can have undulating surfaces which mate in a comb relationship.

Double hidden flexure microactuator for phase mirror array

The complete general solution of nonlinear 1-D undoped Poisson’s equation, in both Cartesian and cylindrical coordinates, is derived by employing a special variable transformation method. A general model platform for various types of emerging multi-gate MOSFETs is further constructed and verified with TCAD simulations. It is shown that this model platform is suitable for analyzing a series of emerging devices, such as double-surrounding-gate, inner-surrounding-gate, and outer-surrounding-gate nanoshell MOSFETs, all of which require different boundary conditions from the conventional gate-all-around nanowire device.

Yijian Chen

Papers

Maskless extreme ultraviolet lithography

Technological Merits, Process Complexity, and Cost Analysis of Self-aligned Multiple Patterning

Fabrication of parallel-plate nanomirror arrays for extreme ultraviolet maskless lithography

Double hidden flexure microactuator for phase mirror array

A General and Transformable Model Platform for Emerging Multi-Gate MOSFETs