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Jun Zhou

Researcher at Anhui University

Publications -  6
Citations -  81

Jun Zhou is an academic researcher from Anhui University. The author has contributed to research in topics: Soft error & Static random-access memory. The author has an hindex of 2, co-authored 6 publications receiving 11 citations.

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Journal ArticleDOI

Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node Upsets

TL;DR: This paper presents two novel radiation-hardened SRAM cell designs, namely S4P8N and S8P4N, with enhanced self-recoverability from single-node upsets (SNUs) and Double-nodeupsets (DNUs), and Simulation results validate the high robustness of the proposed SRAM cells.
Journal ArticleDOI

Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets

TL;DR: This paper presents two novel quadruple cross-coupled memory cell designs, namely Q CCM10T and QCCM12T, with protection against single event upsets (SEUs) and double-node upset (DNUs), and demonstrates the robustness of the proposed memory cells.
Proceedings ArticleDOI

Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications

TL;DR: This paper presents a novel Sextuple Cross-Coupled SRAM cell, namely SCCS cell, which can tolerate both SNUs and DNUs, and Simulation results validate the excellent robustness of the proposed cell.
Journal ArticleDOI

Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications

TL;DR: Simulation results not only confirm the TNU-tolerance of the proposed latches but also demonstrate that the delay-power-area products of the DDETT and LCDDETT latches are reduced by approximately 34% and 58%, respectively.
Proceedings ArticleDOI

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors

TL;DR: Compared with the state-of-the-art hardened SRAM cells, the proposed SESRS cell can reduce read access time by 61.93% on average and reduce power consumption by 49.78% and silicon area by 7.92%, compared with the only existing SRAM cell which can self-recover from all possible DNUs.