http://antonirogalski.com/wp-content/uploads/2011/12/Infrared-detectors-Status-and-trends.pdf

Infrared detectors: status and trends

This paper mainly focuses on the development of the NOR flash memory technology, with the aim of describing both the basic functionality of the memory cell used so far and the main cell architecture consolidated today. The NOR cell is basically a floating-gate MOS transistor, programmed by channel hot electron and erased by Fowler-Nordheim tunneling. The main reliability issues, such as charge retention and endurance, are discussed, together with an understanding of the basic physical mechanisms responsible. Most of these considerations are also valid for the NAND cell, since it is based on the same concept of floating-gate MOS transistor. Furthermore, an insight into the multilevel approach, where two bits are stored in the same cell, is presented. In fact, the exploitation of the multilevel approach at each technology node allows an increase of the memory efficiency, almost doubling the density at the same chip size, enlarging the application range and reducing the cost per bit. Finally, NOR flash cell scaling issues are covered, pointing out the main challenges. Flash cell scaling has been demonstrated to be really possible and to be able to follow Moore's law down to the 130-nm technology generations. Technology development and consolidated know-how is expected to sustain the scaling trend down to 90- and 65-nm technology nodes. One of the crucial issues to be solved to allow cell scaling below the 65-nm node is the tunnel oxide thickness reduction, as tunnel thinning is limited by intrinsic and extrinsic mechanisms.

Introduction to flash memory

Endocrine tumors such as aldosterone-producing adrenal adenomas (APAs), a cause of severe hypertension, feature constitutive hormone production and unrestrained cell proliferation; the mechanisms linking these events are unknown. We identify two recurrent somatic mutations in and near the selectivity filter of the potassium (K+) channel KCNJ5 that are present in 8 of 22 human APAs studied. Both produce increased sodium (Na+) conductance and cell depolarization, which in adrenal glomerulosa cells produces calcium (Ca2+) entry, the signal for aldosterone production and cell proliferation. Similarly, we identify an inherited KCNJ5 mutation that produces increased Na+ conductance in a Mendelian form of severe aldosteronism and massive bilateral adrenal hyperplasia. These findings explain pathogenesis in a subset of patients with severe hypertension and implicate loss of K+ channel selectivity in constitutive cell proliferation and hormone production.

https://science.sciencemag.org/content/sci/331/6018/768.full.pdf

K+ Channel Mutations in Adrenal Aldosterone-Producing Adenomas and Hereditary Hypertension

The aim of this paper is to give a thorough overview of flash memory cells. Basic operations and charge-injection mechanisms that are most commonly used in actual flash memory cells are reviewed to provide an understanding of the underlying physics and principles in order to appreciate the large number of device structures, processing technologies, and circuit designs presented in the literature. New cell structures and architectural solutions have been surveyed to highlight the evolution of the flash memory technology, oriented to both reducing cell size and upgrading product functions. The subject is of extreme interest: new concepts involving new materials, structures, principles, or applications are being continuously introduced. The worldwide semiconductor memory market seems ready to accept many new applications in fields that are not specific to traditional nonvolatile memories.

Flash memory cells-an overview

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

/pdf/active-pixel-sensor-with-intra-pixel-charge-transfer-387ug1605r.pdf

Active pixel sensor with intra-pixel charge transfer

An undesirable image lag with a long time constant was found in the interline CCD image sensor having N+P-junction photodiode (PD). This paper clarifies the image lag mechanism and proposes a new photodiode structure having no image lag. The image lag measurement method and the experimental results are also given. The experimental results quantitatively agreed with the analytical model, in which signal electrons are assumed to be transferred from the PD to the vertical CCD as a small subthreshold current. To eliminate the image lag, a P+NP-structure PD with low donor concentration was proposed, where all the signal electrons can be quickly transferred before the subthreshold condition begins. As a result, the decay lag values of the 1st and the 2nd fields were reduced to half and the decay lags after the 3rd field were not observed.

No image lag photodiode structure in the interline CCD image sensor

THE APPLICATION OF AN overflow drain and barrier positioned beside the photosensitive area? has made it possible to suppress blooming of CCD image sensors. However, this method was found to sacrifice photosensitivity and dynamic range. This paper will describe an interline CCD sensor where the vertical overflow drain is positioned under, rather than beside the photodiode. Thus the cell area can now be used effectively for photoelectron generation and storage, and increased photosensitivity and dynamic range can be maintained. Furthermore, this technique eliminates the blooming phenomenon.

Interline CCD image sensor with an anti blooming structure

An undesirable image lag with a long time constant was found in the interline CCD image sensor having an n+-p-junction photodiode (PD). This paper clarifies the image lag mechanism and proposes a new photodiode structure having very little image lag. The image lag measurement method and the experimental results are also given. The experimental results quantitatively agree with the analytical model, in which signal electrons are assumed to be transferred from the PD to the vertical CCD as a small subthreshold current. To eliminate the image lag, a p+-n-p-structure PD with low donor concentration is proposed, in which all the signal electrons can be quickly transferred before the subthreshold condition begins. As a result, decay lag values for the first and the second fields were reduced to half and no decay lags were observed after the third field.

An interline CCD image sensor with reduced image lag

Clear evidence is presented that the floating gate poly-Si grain size dominates flash memory erase characteristics. Smaller grain size shows a narrower erase distribution. Thus conventional scaling theories should be modified to include that grain size must be shrunk proportional to the cell size. A process technology breakthrough will have to be achieved to form smaller size grains because 16 M will be the maximum capacity using current process technology with this new theory. It is also shown how 64 M flash memories can be achieved without such a technology breakthrough. >

The solution of over-erase problem controlling poly-Si grain size-modified scaling principles for flash memory

New technologies to increase the photo-sensitivity and reduce the shutter voltage of the vertical over-flow-drain (VOD) have been developed for CCD image sensors. The photo-sensitivity was increased 40% by forming an anti-reflection film over the photodiode and reducing the thickness of the p/sup +/-layer formed at the photodiode surface. The VOD shutter voltage was reduced from 31 to 18 V by using an epitaxially grown substrate with double impurity concentration layers.

K. Arai

Papers

No image lag photodiode structure in the interline CCD image sensor

Interline CCD image sensor with an anti blooming structure

An interline CCD image sensor with reduced image lag

The solution of over-erase problem controlling poly-Si grain size-modified scaling principles for flash memory

Technologies to improve photo-sensitivity and reduce VOD shutter voltage for CCD image sensors