Showing papers in "IEEE Transactions on Electron Devices in 1984"

A reliable approach to charge-pumping measurements in MOS transistors

Abstract: A new and accurate approach to charge-pumping measurements for the determination of the Si-SiO 2 interface state density directly on MOS transistors is presented. By a careful analysis of the different processes of emission of electrons towards the conduction band and of holes towards the valence band, depending on the charge state of the interface, all the previously ill-understood phenomena can be explained and the deviations from the simple charge-pumping theory can be accounted for. The presence of a geometric component in some transistor configurations is illustrated and the influence of trapping time constants is discussed. Furthermore, based on this insight, a new technique is developed for the determination of the energy distribution of interface states in small-area transistors, without requiring the knowledge of the surface potential dependence on gate voltage.

Limiting efficiency of silicon solar cells

Abstract: The detailed balance method for calculating the radiative recombination limit to the performance of solar cells has been extended to include free carrier absorption and Auger recombination in addition to radiative losses. This method has been applied to crystalline silicon solar cells where the limiting efficiency is found to be 29.8 percent under AM1.5, based on the measured optical absorption spectrum and published values of the Auger and free carrier absorption coefficients. The silicon is assumed to be textured for maximum benefit from light-trapping effects.

Generalized scaling theory and its application to a ¼ micrometer MOSFET design

Abstract: In this paper we present a generalized scaling theory which allows for an independent scaling of the FET physical dimensions and applied voltages, while still maintaining constant the shape of the electric-field pattern. Thus two-dimensional effects are kept under control even though the intensity of the field is allowed to increase. The resulting design flexibility allows the design of FET's with quarter-micrometer channel length to be made, for either room temperature or liquid-nitrogen temperature. The physical limitations of the scaling theory are then investigated in detail, leading to the conclusion that the limiting FET performances are not reached at the 0.25-µm channel length. Further improvements are possible in the future, provided certain technology breakthroughs are achieved.

High-efficiency silicon solar cells

Abstract: Silicon solar cells are described which operate at energy conversion efficiencies independently measured at 18.7 percent under standard terrestrial test conditions (AM1.5, 100 mW/cm2, 28°C). These are apparently the most efficient silicon cells fabricated to date. The high-efficiency results from a combination of high open-circuit voltage due to the careful attention paid to the passivation of the top surface of the cell; high fill factor due to the high open-circuit voltage and low parasitic resistance losses; and high short-circuit current density due to the use of shallow diffusions, a low grid coverage, and an optimized double layer antireflection coating.

Solar cell contact resistance—A review

Abstract: An overview of ohmic contacts on solar cells is presented The fundamentals of metal-semiconductor contacts are reviewed, including the Schottky approach, Fermi level pinning by surface states, and the mechanisms of thermionic emission, thermionic/field emission, and tunneling for current transport The concept of contact resistance is developed and contact resistance data for several different contact materials on both silicon and gallium arsenide over a range of doping densities are summarized Finally, the requirements imposed by solar cells on contact resistance are detailed

Lucky-electron model of channel hot-electron injection in MOSFET'S

Abstract: The lucky-electron concept is successfully applied to the modeling of channel hot-electron injection in n-channel MOSFET's, although the result can be interpreted in terms of electron temperature as well. This results in a relatively simple expression that can quantitatively predict channel hot-electron injection current in MOSFET's. The model is compared with measurements on a series of n-channel MOSFET's and good agreement is achieved. In the process, new values for many physical parameters such as hot-electron scattering mean-free-path, impact-ionization energy are determined. Of perhaps even greater practical significance is the quantitative correlation between the gate current and the substrate current that this model suggests.

Modified 1/f trapping noise theory and experiments in MOS transistors biased from weak to strong inversion—Influence of interface states

Abstract: Low-frequency 1/f noise in Si n-channel MOSFET's is measured from weak to strong inversion, through the relative spectral density of the drain current fluctuations S_{I}_{D}/I^{2}_{D} . Under specific conditions, a plateau is observed in the variations of S_{I}_{D}/I^{2}_{D} versus the gate voltage in weak inversion followed by a steep decrease in strong inversion. A modified trapping noise theory based on the McWhorter's assumptions and valid in all the working regimes is developed to account for this behavior. Excellent agreement is obtained with the variations of several parameters: gate and drain biases, geometry, oxide and depletion capacitance, temperature, and technologies. The influence of fast interface states is particularly studied and is related to the noise variations and the oxide trap densities.

Limits on the open-circuit voltage and efficiency of silicon solar cells imposed by intrinsic Auger processes

Abstract: Auger recombination processes are shown to impose the most severe intrinsic bounds on the open-circuit voltage and efficiency of silicon solar cells. This applies for both heavily doped and lightly doped material. The upper bound on the open-circuit voltage of a 300- µm-thick silicon cell is 750 mV (AMO, 25°C) irrespective of substrate resistivity. This bound increases to 800 mV for a 20 µm thick cell but decreases to a maximum value of 720 mV for cells thicker than the corresponding minority carrier diffusion length. The corresponding practical bound on cell efficiency is estimated as 25 percent (AM1.5, 100 mW/cm2, 28°C).

Hot-electron-induced photon and photocarrier generation in Silicon MOSFET's

Abstract: The phenomenon of and the physical mechanisms for the generation of minority carriers in the substrate of NMOS and CMOS are studied Secondary impact ionization is not responsible The responsible mechanisms are hot-electron-induced photocarrier generation and, under extreme conditions, forward biasing of the source-substrate junction The photon generation is believed to be due to the bremsstrahlung of the channel hot electrons A theoretical model based on the lucky electron concept and the bremsstrahlung mechanism is proposed The calculated characteristics of photon generation agree well with experimental results About 2 × 10-5photogenerated minority carriers are generated for every (primary) impact-ionization event in NMOSFET Photocarrier-induced leakage current can be fitted with either an inverse square dependence on distance or an exponential dependence with an effective decay length of about 780 µm

The effect of high fields on MOS device and circuit performance

Abstract: A simple analytical model for the MOS device characteristics including the effect of high vertical and horizontal fields on channel carrier velocity is presented. Analytical expressions for the drain current, saturation drain voltage, and transconductance are developed. These expressions are used to examine the effect of scaling the channel length, the gate dielectric thickness, and the bias voltage on device characteristics. Experimental results from various geometry MOS devices are used to verify the trends predicted by the model. Using the physical understanding provided by the model, we examine the effect of device geometry scaling on circuit performance. We suggest that for gate capacitance-limited circuits one should reduce the channel length, and for parasitic capacitance-limited circuits one should reduce the gate dielectric thickness to improve circuit performance.

The insulated gate transistor: A new three-terminal MOS-controlled bipolar power device

Abstract: A new three-terminal power device, called the insulated gate transistor (IGT), with voltage-controlled output characteristics is described. In this device, the best features of the existing families of bipolar devices and power MOSFET's are combined to achieve optimal device characteristics for low-frequency power-control applications. Devices with 600-V blocking capability fabricated using a vertical DMOS process exhibit 20 times the conduction current density of an equivalent power MOSFET and five times that of an equivalent bipolar transistor operating at a current gain of 10. Typical gate turn-off times have been measured to range from 10 to 50 µs.

Contact resistance: Its measurement and relative importance to power loss in a solar cell

Abstract: The concept of contact resistivity is discussed briefly and a technique for its measurement is presented. This technique allows for resistive contact material and for the possibility that the semiconductor sheet resistance beneath the contact differs from the semiconductor sheet resistance beside the contact. The test pattern is unique in that the effects of contact resistance are accumulated over the pattern, nearly unencumbered by voltage and current probes which might otherwise influence the current flow. Measurements of contact resistivities for typical solar cell metallizations using this technique are reported to be in the mid 10-6Ω-cm2range. The relative importance of contact resistance compared to other sources of power loss in a solar cell is determined for a typical contact system. Expressions derived in order to make this comparison are useful for evaluating and optimizing a solar cell contact system. Values of series resistance calculated using these expressions are compared with measured values.

New infrared detector on a silicon chip

Abstract: We report a single-crystal Si-Ge structure which works as an efficient photodetector in the wavelength region of up to 1.5 µm. The multilevel structure is grown by molecular-beam epitaxy on an n-type 3-in silicon substrate and consists of the following layers: n+silicon (1000 A), n+Ge x Si 1 - x alloy (1800 A, graded in ten steps from x = 0 to x = 1 ), n+germanium (1.25 µm), undoped germanium (2.0 µm), and p+germanium (2500 A). Top three layers form a germanium p-i-n diode, which is removed from the Ge-Si interface by a buffer layer of high conductivity. An advantage of this structure is that its performance is insensitive to material defects in the buffer layers. Moreover, transmission electron microscopy shows that the density of dislocations introduced by lattice mismatch at the Ge-Si interface falls off with the separation from the interface. Our first experimental structures do exhibit the characteristics of a germanium p-i-n diode. The spectral response curves agree with those given in the literature for germanium, both at room and liquid nitrogen temperatures. For the incident light wavelength of 1.45 µm we have measured a quantum efficiency of 41 percent at T = 300 K. we believe that our approach opens an attractive possibility of fabricating complete infrared optoelectronic systems on a silicon chip.

Method for determining the emitter and base series resistances of bipolar transistors

Abstract: A simple method for determining both the emitter and the base series resistances of bipolar transistors from the measured I - V characteristics is described. The method is based on the observation that deviation of the base current from the ideal \exp (qV_{BE}/kT) behavior at high currents can be attributed solely and relatively simply to series resistances. Series resistances determined by this method are given for sample high-speed digital bipolar transistors.

Modulation-doped GaAs/AlGaAs heterojunction field-effect transistors (MODFET's), ultrahigh-speed device for supercomputers

Abstract: In the past few years, a new transistor has appeared on the scene, made of GaAs and AlGaAs, which now holds the record as the fastest logic switching device, switching at speeds of close to ten trillionths of a second (10 ps). The device evolved from the work on GaAs-AlGaAs superlattices (thin alternating layers of differing materials sharing the same crystalline lattice) pioneered by L. Esaki and R. Tsu at IBM in the late 1960's. They realized that high mobilities in GaAs could be achieved if electrons were transferred from the doped and wider band-gap AlGaAs to an adjacent undoped GaAs layer, a process now called modulation doping. R. Dingle, H. L. Stormer, A. C. Gossard, and W. Wiegmann of AT&T Bell Labs, working independently, were the first to demonstrate high mobilities obtained by modulation doping in 1978, in a GaAs-AlGaAs superlattice. Realizing that such a structure could form the basis for a high-performance field-effect transistor (Bell Labs Patent 4163237, filed on April 24, 1978), researchers at various labs in the United States (Bell Labs, University of illinois, and Rockwell), Japan (Fujitsu), and France (Thomson CSF) began working on this device. In 1980, the first such device with a reasonable microwave performance was fabricated by the University of Illinois and Rockwell, which they called a modulation-doped FET or MODFET. The same year Fujitsu reported the results obtained in a device with a 400-µm gate which they called the "high electron mobility transistor" or HEMT, in the open literature. Thomson CSF published shortly thereafter calling their realization a "two-dimensional electron gas FET" or TEGFET, and Bell Labs followed, using the name "selectively doped heterojunction transistor" or SDHT. These names are all descriptive of various aspects of the device operation as we will discuss in the text. For the sake of internal consistency will call it MODFET, hereafter. In this paper we review the principals of MODFET operation, factors affecting its performance, optimization of the device, and comparison with other high-performance compound and elemental semiconductor devices. Finally, the remaining problems and future challenges are pointed out.

An investigation of the effect of graded layers and tunneling on the performance of AlGaAs/GaAs heterojunction bipolar transistors

Abstract: We present the results of theoretical and experimental studies of the heterojunction bipolar transistor. Our calculations are based on a new thermionic field-diffusion model which takes into account the dependence of the emitter efficiency on the height of the interface conduction band spike and tunneling across the spike. Based on this theory we derive analytical expressions for the current-voltage characteristics and relate the short-circuit common emitter current gain to the material parameters, doping levels, grading length, and device temperature. We demonstrate that the thermoemission transport across the interface spike limits the rate of increase in the collector current with the emitter-base voltage and, as a consequence, the maximum common emitter current gain. Tunneling also plays an important role, especially for abrupt heterojunctions. Our calculations reveal an important role played by grading of the composition of the emitter region in the vicinity of the heterointerface. Such grading decreases the barrier height at the interface and greatly enhances the emitter injection efficiency.

Point-contact silicon solar cells

Abstract: A new type of silicon photovoltaic cell designed for high-concentration applications is presented. The device is called the point-contact-cell and shows potential for achieving energy conversion efficiencies in the neighborhood of 28 percent at the design operating point of 500× geometric concentration and 60°C cell temperature. This cell has alternating n and p regions that form a polkadot array on the bottom surface. A two-layermetallization on the bottom provides contact. Initial experimental results have yielded a cell with 20-percent efficiency at a concentration of 88.

The physics and modeling of heavily doped emitters

Abstract: The physics of minority-carrier injection and internal quantum efficiency of heavily doped emitters is studied through a novel computer simulation. It is shown that in the shallow emitters of modern devices, the transport of carriers through the bulk of the emitter, and the surface recombination rate are the dominant mechanisms controlling the minority-carrier profile. Carrier recombination in the bulk of the emitter only produces a small perturbation of this profile. This observation permits us to develop a simple and accurate analytical model for the saturation current and internal quantum efficiency of shallow emitters.

The evolution of power device technology

Abstract: Power semiconductor devices and their associated technology have come a long way from their beginnings with the invention of the bipolar transistor in the late 1940's. Presently, the spectrum of what are referred to as "power devices" span a very wide range of devices and technology from the massive 4 in, 3000-A thyristor to the high-voltage integrated circuit and the power MOSFET, a device of VLSI complexity containing up to 150 000 separate transistors. In this paper, the past, present, and future of power devices will be reviewed. The first section will be a historical perspective indicating the key events and developments of the past that brought the power devices of today to their present state. The second section of the paper will review the technology and characteristics of bipolar power devices with separate subsections on thyristors, the gate turnoff thyristor (GTO), and the bipolar transistor. Within the thyristor subsection there will be discussions of the phase control thyristor, the inverter thyristor, the asymmetric thyristor (ASCR) the reverse conducting thyristor (RCT), the gate-assisted turn-off thyristor (GATT), and finally the light-triggered thyristor (LTT). The third section of the paper is devoted to the new field of integrated power devices and will review the evolution to the present power MOS devices including the power MOSFET, the insulated gate transistor (IGT), and the high voltage IC (HVIC). The last section of the paper reviews the future of power devices with projections as to future ratings of power devices for both the traditional bipolar devices, such as the thyristor, GTO, and bipolar transistor, as well as the integrated devices such as the MOSFET and the IGT. In case of the former, in particular the thyristor, the maximum device ratings will be tied to the availability of large area float zone material, currently difficult to obtain in the high resistivities needed for power devices. In the case of integrated devices, the maximum ratings will be limited by the maximum die area for which acceptable device yields can be obtained. This is identical to the situation for conventional IC's since much of the unit processing is the same.

The phase-shifting mask II: Imaging simulations and submicrometer resist exposures

Abstract: Submicrometer optical lithography is possible with conventional projection cameras when the mask controls the phase of the light at the object plane. Two-dimensional imaging simulations for the Mann 4800 projection camera show that the maximum spatial frequency for 60-percent contrast increases from 640 1/mm to 896 1/mm. The geometrical quality of the images of typical microcircuit patterns was shown to be acceptable for feature sizes of 0.7, 0.6, and 0.5 µ, respectively, and various parameters of the irradiance patterns were calculated. Exposures were made using a high-performance two-layer photoresist system and a mask containing patterns similar to those in the simulation. The phase-shifting mask was shown to increase exposure latitude and to produce a 95-percent yield of 833 1/mm (0.6 µ line and gap) patterns, whereas the transmission mask gave a 7-percent yield. Half micrometer features were patterned with a 22-percent yield using 0.436-µ light.

An improved forward I-V method for nonideal Schottky diodes with high series resistance

Abstract: Two methods are described to obtain the value of the series resistance (R) of a Schottky diode from its forward I-V characteristic. The value of R is then used to plot the curve ln ( I ) versus V_{D} (= V - IR) which becomes a straight line even if ln (I) versus V does not. The ideality factor n and the Schottky-barrier height \Phi_{B0} of the diode then follow from the standard procedure. The main advantages of the methods are: 1) a linear regression can be used to calculate the value of R , 2) many data points are used over the whole data range which raises the accuracy of the results, and 3) the validity of constant R assumption can be checked by the linearity of the ln (I) versus V D curve. The methods are illustrated on the experimental data of a real diode.

FIPOS (Full Isolation by Porous Oxidized Silicon) technology and its application to LSI's

Abstract: Processing steps of FIPOS (Full Isolation by Porous Oxidized Silicon) technology and its application to LSI's are presented, FIPOS technology realizes a silicon-on-insulator structure, utilizing thick porous oxidized silicon and donors produced by proton implantation. New processing steps are proposed which provides small surface step and are suitable for LSI fabrication. Formation conditions of thick porous oxidized silicon are established by density control technique for porous silicon using a newly developed anodization system. CMOS devices are fabricated in isolated silicon layers and it is shown that the characteristics of n-channel and p-channel MOSFETS's are sufficient for application to CMOS LSI's. A FIPOS/CMOS logic array with 1.3K gate is successfully fabricated, which shows a higher speed and lower power dissipation than the gates fabricated by bulk CMOS technology. These results indicate that FIPOS technology is very useful for realizing high-performance CMOS LSI's.

MOSFET degradation due to stressing of thin oxide

Abstract: Oxide and interface traps in 100 A SiO 2 created by Fowler-Nordheim tunneling current have been investigated using capacitor C-V, I-V, and transistor I-V measurements. The net oxide trapped charge is initially positive due to hole trapping near the anode interface and, at sufficiently high fluence, it becomes negative due to the trapping of electrons with a centroid of 60 A from the injector (cathode) interface. Interface traps (Surface states) are created by tunneling electrons flowing to and from the substrate. The interface-trap energy distribution gives a distinct peak at 0.65 eV above the valence band edge. The positive charge trapping and interface traps generation saturate at high electron fluence, but not the electron trap generation. The generation rates for electron traps and interface traps are weak functions of tunneling current density over the range tested. The interface traps cause degradations in subthreshold current slope and surface electron mobility. The threshold-voltage shift can be either positive or negative under the combined influence of the oxide charges and the interface charges.

Polycrystalline thin-film CuInSe 2 /CdZnS solar cells

Abstract: The fabrication and properties of polycrystalline, CuInSe 2 thin-film solar cells based upon a heterojunction device structure of P-type CuInSe 2 and N-type CdS or mixed CdZnS are described. A photovoltaic conversion efficiency of 11 percent is reported for a CuInSe 2 / CdZnS cell of 1-cm2area when tested under simulated AM1 illumination (ELH lamp). While the highest efficiency cells have been prepared on Mo-metallized, polycrystalline alumina substrates, good cell performance is also presented for cells fabricated on low-cost glass substrates. The vacuum deposited selenide and sulfide films are reported to exhibit strong columnar growth features throughout the critical junction region. The spectral response of the cells is described as being relatively flat from 1100 to 600 nm with very high quantum yields(> 0.8). Photoluminescence emission data on the CuInSe 2 thin-film excited with a He-Ne laser is presented. In general, selenide films producing a good cell performance are reported to exhibit spectra with two or three major broad-band emissions.

Charge injection transistor based on real-space hot-electron transfer

Abstract: We describe a new transistor based on hot-electron transfer between two conducting layers separated by a potential barrier. The mechanism of its operation consists of controlling charge injection over the barrier by modulating the electron temperature in one of the layers. This physical principle is different from those employed in all previous three-terminal amplifying devices-which are based either on the modulation of a potential barrier (vacuum triode, bipolar transistor, various analog transistors) or on the modulation of charge in a resistive channel (field effect transistors). In contrast to this, the present device can be compared to a hypothetical vacuum diode whose cathode has an effective electron temperature which is controlled without inertia by an input electrode ("cathode heater"). The device has been implemented in an AlGaAs/GaAs heterojunction structure. One of the conducting layers is realized as an FET channel, the other as a heavily doped GaAs substrate. The layers are separated by an Al x Ga 1 - x As graded barrier. Application of a source-to-drain field leads to a heating of channel electrons and charge injection into the substrate. The substrate thus serves as an anode and the FET channel represents a hot-electron cathode, whose effective temperature is controlled by the source-to-drain field. Operation of the charge injection transistor is studied at 300, 77, and 4.2 K. At 77 K the existence of power gain is demonstrated experimentally with the measured value of the mutual conductance g m reaching 280 mS/mm (at 300 K, g m ≈ 88 mS/mm). The fundamental limit on the device speed of operation is analyzed and shown to be determined by the time of flight of electrons across a high-field region of spatial extent ∼ 10-5cm. Practical ways of approaching this limit are discussed. The process of hot-electron injection from the channel is studied experimentally at 77 and 4.2 K with the purpose of measuring the electron temperature in the channel at different bias conditions. For not too high substrate bias the electron temperature in the channel is found to be proportional to the square of the heating voltage.

Piezoelectric effects in GaAs FET's and their role in orientation-dependent device characteristics

Abstract: Elastic stresses are frequently induced in GaAs substrates during the fabrication of FET's, particulariy in the vicinity of windows in dielectric overlayers. It is shown here that these stresses can produce piezoelectric charge densities of such magnitude to appreciably shift the pinchoff voltage and saturation current of FET's. These shifts are of opposite sign for FET's oriented along [011] and [011] directions on

The thin film transistor—A late flowering bloom

Abstract: The thin film transistor was the first solid-state amplifier ever patented, but has found no practical application until quite recently. The history of this device is traced from the early and unsuccessful Bell Labs experiments, through its brief resurgence in the 1960's as a competitor to the MOSFET; its second disappearance from public view followed by years of hibernation at Westinghouse Labs; its emergence in the 1970's as a candidate for forming very large area integrated circuits for flat panel displays, leading to the present era of intensive, worldwide exploitation as a device which has at last found a suitable problem to solve. The present state of the art of TFT's made of CdSe, poly- and amorphous silicon is reviewed, particularly as it pertains to their current predominant use in high resolution/high performance liquid crystal displays, followed by some views on the future for TFT's in active matrices and, possibly, in other "human size" or macro-electronic components and systems.

Comparison of experimental and theoretical results on polysilicon emitter bipolar transistors

Abstract: Two types of polysilicon emitter transistors have been fabricated using identical processing except for the surface treatment prior to polysilicon deposition. The first type was given a dip etch in buffered hydrofluoric acid, which was intended to remove any interfacial oxide, while the second type was given an RCA clean, which was intended to grow an interfacial oxide of known thickness. Detailed electrical measurements have been made on these devices including the temperature dependence of the gain over a wide temperature range. The transistors given an RCA clean have gains approximately five times higher than those given an HF etch. In addition, the temperature dependence of the gain is different for the two types, with the HF devices exhibiting a much stronger dependence at high temperatures than the RCA devices. A detailed comparison is made with the theory and it is shown that the characteristics of the HF devices can largely be explained using a transport theory, while those of the RCA devices can be fully explained using a modified tunneling theory.

Thick-film metallization for solar cell applications

Abstract: The use of an integral printing technique for the fabrication of silicon solar cells is attractive due to its throughput rate, materials utilization, and modular, automatable design. The transfer of this technology from single crystal to semicrystalline silicon requires a significant amount of process optimization. Processing parameters found to be critical include the optimum glass frit content in the silver-based inks, the silver ink firing temperature, and the formation of the back-surface field using screen-printed aluminum layers. Open-circuit voltages as high as 617 mV have been achieved using a novel BSF approach on 4-in wafers. Important mechanisms controlling ink contact resistance, ink sheet resistivity, and ohmic contact on and silicon materials are discussed in this paper. The solar cell stability is a function of the glass frit and the firing temperature of the silver-based inks. Finally, a simple economic analysis, based on the IPEG technique, indicates that screen printing is a cost-effective option when the cell manufacturing is done on a large scale.

On the collapse of drain I-V characteristics in modulation-doped FET's at cryogenic temperatures

Abstract: The collapse of the drain current-voltage characteristics of modulation-doped field-effect transistors (MODFET's) at cryogenic temperatures, previously thought to be unavoidable, has been investigated. The results indicate that the mechanism responsible for the collapse is dependent on both the device fabrication steps and the parameters of crystal growth. Bulk Al x Ga 1 - x AsFET's fabricated in our laboratory exhibited little or no collapse in the I-V characteristics at 77 K in the dark, demonstrating that the mechanism responsible for this pheonomenon is not related to problems associated with contacting Al x Ga 1 - x As. MODFET's with proper fabrication and growth procedures showed no collapse. In those devices exhibiting no collapse, the source resistance exhibited a substantial decrease upon cooling. At 300 K source resistances slightly over 1.0 Ω . mm with a transconductance of 170 mS/mm were obtained. Upon cooling, the source resistance decreased to 0.5 Ω . mm with a transconductance of 280 mS/mm. These results demonstrate that MODFET's will exhibit enhanced performance at 77 K without exposure to light. Specific contact resistivities measured at room temperature ranged from 2 × 10-7to 2 × 10-6Ω cm2depending on the structural parameters.