A forward-facing vision system for a vehicle includes a forward-facing camera disposed in a windshield electronics module attached at a windshield of the vehicle and viewing through the windshield. A control includes a processor that, responsive to processing of captured image data, detects taillights of leading vehicles during nighttime conditions and, responsive to processing of captured image data, detects lane markers on a road being traveled by the vehicle. The control, responsive to lane marker detection and a determination that the vehicle is drifting out of a traffic lane, may control a steering system of the vehicle to mitigate such drifting, with the steering system manually controllable by a driver of the vehicle irrespective of control by the control. The processor, based at least in part on detection of lane markers via processing of captured image data, determines curvature of the road being traveled by the vehicle.

Vision system for vehicle

The pinned photodiode is the primary photodetector structure used in most CCD and CMOS image sensors. This paper reviews the development, physics, and technology of the pinned photodiode.

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A Review of the Pinned Photodiode for CCD and CMOS Image Sensors

A driver assistance system for a vehicle includes an imaging device having a field of view forward of a vehicle and in a direction of travel of the equipped vehicle, an image processor operable to process image data captured by the imaging device, and a global positioning system operable to determine a geographical location of the vehicle. The equipped vehicle includes an adaptive speed control system for controlling the speed of the equipped vehicle. The adaptive speed control system may reduce the speed of the equipped vehicle responsive at least in part to a detection of a curve in the road ahead of the equipped vehicle via processing by the image processor of image data captured by the imaging device.

Driver assistance system for vehicle

An undesirable image lag with a long time constant was found in the interline CCD image sensor having N+P-junction photodiode (PD). This paper clarifies the image lag mechanism and proposes a new photodiode structure having no image lag. The image lag measurement method and the experimental results are also given. The experimental results quantitatively agreed with the analytical model, in which signal electrons are assumed to be transferred from the PD to the vertical CCD as a small subthreshold current. To eliminate the image lag, a P+NP-structure PD with low donor concentration was proposed, where all the signal electrons can be quickly transferred before the subthreshold condition begins. As a result, the decay lag values of the 1st and the 2nd fields were reduced to half and the decay lags after the 3rd field were not observed.

No image lag photodiode structure in the interline CCD image sensor

A chip implementing random scan was designed, fabricated, and tested. The chip covers the basic requirements for random access and separation between the sampling and reading processes. In this way, a repeated reading of any pixel at any time can take place. The chip includes an 80*80 matrix of basic cells. Each cell consists of two stages: The first is based on a switch, whereas the second includes a buffer. The chip was fabricated in a 3- mu m CMOS process. It was found to operate functionally. However, the use of a standard process gave rise to the crosstalk phenomenon, which has yet to be overcome. >

A random access photodiode array for intelligent image capture

THE APPLICATION OF AN overflow drain and barrier positioned beside the photosensitive area? has made it possible to suppress blooming of CCD image sensors. However, this method was found to sacrifice photosensitivity and dynamic range. This paper will describe an interline CCD sensor where the vertical overflow drain is positioned under, rather than beside the photodiode. Thus the cell area can now be used effectively for photoelectron generation and storage, and increased photosensitivity and dynamic range can be maintained. Furthermore, this technique eliminates the blooming phenomenon.

Interline CCD image sensor with an anti blooming structure

A ⅔-in 384 (H) × 490 (V) element interline CCD image sensor with a new antiblooming structure was developed. Blooming was suppressed without sacrificing photosensitivity and dynamic range by means of a vertical overflow drain positioned under (rather than beside) a photodiode. For 10-percent vertical height illumination the smear signal was reduced to 0.05 percent of the illumination signal. Well-balanced performance, namely, large dynamic range (72 dB), low random noise (65 rms noise electrons per charge packet), high-contrast transfer functions for horizontal and vertical directions, and a spectral response similar to the luminous efficiency curve were obtained under moderate operating conditions.

Interline CCD image sensor with an antiblooming structure

HIGH-RESOLUTION TV CAMERAS are essential to home VTRs, industrial TV systems, broadcasting systems, and future high-definition TV systems. To provide cameras, solid-state image sensors are expected to be the most suitable devices, affording performance superior to that available from most of the current vidicon type pickup tubes. However, as far as the resolution is concerned, existing solid-state image sensors’ >2 are still inferior to vidicon pickup tubes. In the design of practical high-resolution solid-state image sensors, it is important to reduce the cell size to one half of that of the conventional device’, and also maintain a wide dynamic range and high sensitivity; i.e., high signal-to-noise ratio. Therefore, signal-handling capability per unit area for both photodiode (PD) and vertical CCD (VCCD) shift registers must be ideally doubled, and noise dominated by the output amplifier must be lowered. This paper will describe a high resolution interline CCD (HRIL-CCD) image sensor which includes 768 pixels in the horizontal direction and 490 pixels in the vertical direction. The overall die size of this sensor is the same as the conventional CCD models’. The HRIL-CCD image sensor was fabricated on a 20-30&m N-type silicon substrate using three-level polysilicon technology and 1 . 5 ~ rule fine pattern process. Image area measures 8.8(H) x 6.6(V) mm, applicable to a 2/3” vidicon lens view field. Unit cell size is 11.5(H) x 13.5(V) p. The aperture ratio is about 40%. A cross sectional view of a unit cell of the image sensor employing a vertical overflow drain’ is shown in Figure 1. The buried channel V-CCD shift register is made of a thick, highly doped P-well. The N-region of the PD is formed in a shallow, lightly doped P-layer which is a lateral diffused region of the above thick, highly doped P-well. Therefore, excess charge, which can be controlled by a substrate voltage, overflows through the laterally diffused P-layer into an N-type silicon substrate to eliminate blooming, while on the other hand, the entire P-well region under the V-CCD shift register is kept undepleted at this substrate voltage. Another advantage of this structure is that a unit cell with smaller size can also be realized by adjusting both dosage and depth of the P-well. The 3 . 3 ~ channel width of the V-CCD shift register was chosen to maximize the PD area. The depth of the buried channel for the V-CCD shigt register was designed to be as shallow as possible ( 0 . 5 ~ ) to obtain as much transferable signal charge as possible. Moreover, the thickness of Si02 for cell isolation has been thinned (about 0 . 3 ~ ) to reduce bird‘s beak intrusion, and also to suppress field-stress

A CCD image sensor with 768&#215;490 pixels

The charge coupled device has a buried type charge transfer region and a charge-voltage converting region in a semiconductor substrate. The charge-voltage converting region is formed in the conductivity type opposite to the substrate and includes a high concentration portion at longitudinal center and low concentration portions at both sides of the high concentration portion.

Output detector of a charge coupled device

A 1/2-inch format 768(H) × 492(V) pixel interline CCD image sensor has been developed. Unit cell dimension is as small as 8.4(H) × 9.8(V) µm. In order to realize such a high density device, various technologies have been developed, i.e., (1) dual channel horizontal CCD registers, (2) single p-well vertical overflow drain, (3) High-Capacitance p-well structure and (4) Inverted-LOCOS channel isolation process. Experimental results show the effectiveness of the technologies used.

T. Kamata

Papers

Interline CCD image sensor with an anti blooming structure

Interline CCD image sensor with an antiblooming structure

A CCD image sensor with 768×490 pixels

Output detector of a charge coupled device

1/2-Inch 768(H)×492(V) pixel CCD image sensor

T. Kamata

Papers

Interline CCD image sensor with an anti blooming structure

Interline CCD image sensor with an antiblooming structure

A CCD image sensor with 768&#215;490 pixels

Output detector of a charge coupled device

1/2-Inch 768(H)&#215;492(V) pixel CCD image sensor

A CCD image sensor with 768×490 pixels

1/2-Inch 768(H)×492(V) pixel CCD image sensor