Nanowire (NW) devices, particularly the gate-all-around (GAA) CMOS architecture, have emerged as the front-runner for pushing CMOS scaling beyond the roadmap. These devices offer unique advantages over their planar counterparts which make them feasible as an option for 22 -nm and beyond technology nodes. This paper reviews the current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories. We also take a glimpse into applications of NWs in the ldquomore-than-Moorerdquo regime and briefly discuss the application of NWs as biochemical sensors. Finally, we summarize the status and outline the challenges and opportunities of the NW technology.

Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications

Understanding interactions between light and matter is central to many fields, providing invaluable insights into the nature of matter. In its own right, a greater understanding of light-matter coupling has allowed for the creation of tailored applications, resulting in a variety of devices such as lasers, switches, sensors, modulators, and detectors. Reduction of optical mode volume is crucial to enhancing light-matter coupling strength, and among solid-state systems, self-assembled semiconductor and hybrid-plasmonic nanowires are amenable to creation of highly-confined optical modes. Following development of unique spectroscopic techniques designed for the nanowire morphology, carefully engineered semiconductor nanowire cavities have recently been tailored to enhance light-matter coupling strength in a manner previously seen in optical microcavities. Much smaller mode volumes in tailored hybrid-plasmonic nanowires have recently allowed for similar breakthroughs, resulting in sub-picosecond excited-state lifetimes and exceptionally high radiative rate enhancement. Here, we review literature on light-matter interactions in semiconductor and hybrid-plasmonic monolithic nanowire optical cavities to highlight recent progress made in tailoring light-matter coupling strengths. Beginning with a discussion of relevant concepts from optical physics, we will discuss how our knowledge of light-matter coupling has evolved with our ability to produce ever-shrinking optical mode volumes, shifting focus from bulk materials to optical microcavities, before moving on to recent results obtained from semiconducting nanowires.

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Tailoring light-matter coupling in semiconductor and hybrid-plasmonic nanowires.

For several years, graphene has been the focus of much attention due to its peculiar characteristics, and it is now considered to be a representative 2-dimensional (2D) material. Even though many research groups have studied on the graphene, its intrinsic nature of a zero band-gap, limits its use in practical applications, particularly in logic circuits. Recently, transition metal dichalcogenides (TMDs), which are another type of 2D material, have drawn attention due to the advantage of having a sizable band-gap and a high mobility. Here, we report on the design of a complementary inverter, one of the most basic logic elements, which is based on a MoS2 n-type transistor and a WSe2 p-type transistor. The advantages provided by the complementary metal-oxide-semiconductor (CMOS) configuration and the high-performance TMD channels allow us to fabricate a TMD complementary inverter that has a high-gain of 13.7. This work demonstrates the operation of the MoS2 n-FET and WSe2 p-FET on the same substrate, and the electrical performance of the CMOS inverter, which is based on a different driving current, is also measured.

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A high-performance complementary inverter based on transition metal dichalcogenide field-effect transistors

In this paper, a detailed 3-D numerical analysis is carried out to study and evaluate CMOS logic device and circuit performance of gate-all-around (GAA) Si nanowire (NW) field-effect transistors (FETs) operating in sub-22-nm CMOS technologies. Employing a coupled drift-diffusion room temperature carrier transport formulation, with 2-D quantum confinement effects, we numerically simulate Si GAA NWFET electrical characteristics. The simulation predictions, on the device performance, short channel effects, and their dependence on NW geometry scaling, are in good agreement with the Si NWFET experimental data reported in literature. Superior electrostatic integrity, OFF-state device performance, lower circuit delays, and faster switching in the Si GAA NWFET-based CMOS circuits are numerically demonstrated in comparison with an Si-on-insulator FinFET. The mixed-mode numerical simulations also predict low supply voltage operations for the Si NWFET-based logic circuits.

CMOS Logic Device and Circuit Performance of Si Gate All Around Nanowire MOSFET

In this paper, we study the impact of surface roughness and its combination with random discrete dopants on the current variability in nanometer-scale nanowire metal-oxidesemiconductor field-effect transistors. It is shown that these two variability sources cannot be regarded as independent in their effect on transport. Interface roughness results in body thickness fluctuations and scattering, which degrades transistor performance. This paper extends our previous study, in which we concentrated only on the impact of random discrete dopants in the source/drain regions in the same type of devices that lead to current variability. We have simulated ensembles of 30 devices, which differ due to the physical manifestation of the variability sources, including the detailed microscopic pattern of the interface in the channel and the number and configuration of discrete dopants in the source/drain regions. An ensemble of devices, with rough interfaces and continuous doping, has first been simulated to differentiate the effect of the interface roughness from the random discrete dopants before considering the combined case. It was found that, in some peculiar cases, the surface roughness induced resonant structures inside the device, producing quasibound states. These resonant states are similar to those related to individual discrete dopants in our previous study. We found that there is strong correlation between the microscopic patterns of the interface and the device performance due to the non-self-averaging of the microscopic features, which plagues devices with small channel lengths. The surface roughness induces a threshold voltage shift and decreases the ON-current of the device due to scattering. In the fully 3-D nonequilibrium Green's function formalism, both effects are combined in the propagation of the electron wave through the device. We have extracted the surface roughness related scattering contribution and estimated the associated mobility.

Variability in Si Nanowire MOSFETs Due to the Combined Effect of Interface Roughness and Random Dopants: A Fully Three-Dimensional NEGF Simulation Study

We present the monolithic integration of gate-all-around (GAA) Si-nanowire FETs into CMOS logic using top-down approach. Inverters are chosen as the test vehicles for demonstration. Empirically optimized designs show sharp ON–OFF transitions with high voltage-gains (e.g., Δ V OUT /Δ V IN up to ∼45) and symmetric pull-up and pull-down characteristics. The matching of the drive currents of n- and p-MOSFETs is achieved using different number of nanowire channels for N- and P-MOS transistors. The inverter maintains its good transfer characteristics and noise margins for wide range of V DD tested down to 0.2 V. The detailed experimental characterization is discussed along with the electrical characteristics of the individual transistors comprising the inverter. The performances of the inverters are discussed vis-a-vis those reported in the literature using advanced non-classical device architectures such as FinFETs. The integration potential of GAA Si-nanowire transistors to realize CMOS circuit functionality using top-down approach is thus demonstrated.

Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach

We present vertical gate-all-around (GAA) silicon nanowire transistors on bulk silicon wafer utilizing fully CMOS compatible technology. High aspect ratio (up to 50:1) vertical nanowires with diameter down to ~ 20 nm are achieved from lithography and dry-etch defined Si-pillars with subsequent oxidation. The surrounding gate length is controlled using etch back of the sacrificial oxide. n- and p-MOS devices thus fabricated with gate length ~ 120 nm to 150 nm showed excellent transistor characteristics with large drive current per wire, high Ion/Ioff ratio (~ 107), good subthreshold slope (~ 80 mV/dec) and low DIBL (~ 20 mV/ V). Along with good electrical characteristics, the use of low cost bulk wafers, and simple gate definition process steps could make this device a suitable candidate for next generation technology nodes.

CMOS compatible Gate-All-Around Vertical silicon-nanowire MOSFETs

We present the monolithic integration of gate-all-around (GAA) Si-nanowire FETs into CMOS logic using top-down approach. Inverters are chosen as the test vehicles for demonstration. Empirically optimized designs show sharp ON-OFF transitions with high voltage-gains (e.g., ΔV OUT /ΔV IN up to ∼45) and symmetric pull-up and pull-down characteristics. The matching of the drive currents of n- and p-MOSFETs is achieved using different number of nanowire channels for N- and P-MOS transistors. The inverter maintains its good transfer characteristics and noise margins for wide range of V DD tested down to 0.2 V. The detailed experimental characterization is discussed along with the electrical characteristics of the individual transistors comprising the inverter. The performances of the inverters are discussed vis-a-vis those reported in the literature using advanced non-classical device architectures such as FinFETs. The integration potential of GAA Si-nanowire transistors to realize CMOS circuit functionality using top-down approach is thus demonstrated.

K.D. Buddharaju

Papers

Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach

CMOS compatible Gate-All-Around Vertical silicon-nanowire MOSFETs

Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach