Journal ArticleDOI
Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach
K.D. Buddharaju,Navab Singh,S.C. Rustagi,Selin H. G. Teo,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +6 more
TLDR
In this article, the integration potential of gate-all-around (GAA) Si-nanowire transistors to realize CMOS circuit functionality using top-down approach is demonstrated.Abstract:
We present the monolithic integration of gate-all-around (GAA) Si-nanowire FETs into CMOS logic using top-down approach. Inverters are chosen as the test vehicles for demonstration. Empirically optimized designs show sharp ON–OFF transitions with high voltage-gains (e.g., Δ V OUT /Δ V IN up to ∼45) and symmetric pull-up and pull-down characteristics. The matching of the drive currents of n- and p-MOSFETs is achieved using different number of nanowire channels for N- and P-MOS transistors. The inverter maintains its good transfer characteristics and noise margins for wide range of V DD tested down to 0.2 V. The detailed experimental characterization is discussed along with the electrical characteristics of the individual transistors comprising the inverter. The performances of the inverters are discussed vis-a-vis those reported in the literature using advanced non-classical device architectures such as FinFETs. The integration potential of GAA Si-nanowire transistors to realize CMOS circuit functionality using top-down approach is thus demonstrated.read more
Citations
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Journal ArticleDOI
Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications
Navab Singh,K.D. Buddharaju,Sanjeev Kumar Manhas,Ajay Agarwal,S.C. Rustagi,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +7 more
TL;DR: The current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories are reviewed and the challenges and opportunities are outlined.
Journal ArticleDOI
Tailoring light-matter coupling in semiconductor and hybrid-plasmonic nanowires.
TL;DR: Light-matter coupling has evolved with the ability to produce ever-shrinking optical mode volumes, shifting focus from bulk materials to optical microcavities, before moving on to recent results obtained from semiconducting nanowires.
Journal ArticleDOI
A high-performance complementary inverter based on transition metal dichalcogenide field-effect transistors
TL;DR: This work reports on the design of a complementary inverter, one of the most basic logic elements, which is based on a MoS2 n-type transistor and a WSe2 p- type transistor, which has a high-gain of 13.7.
Journal ArticleDOI
CMOS Logic Device and Circuit Performance of Si Gate All Around Nanowire MOSFET
Kaushik Nayak,Mohit Bajaj,Aniruddha Konar,Philip J. Oldiges,Kenji Natori,Hiroshi Iwai,Kota V. R. M. Murali,Valipe Ramgopal Rao +7 more
TL;DR: In this article, a detailed 3D numerical analysis is carried out to study and evaluate CMOS logic device and circuit performance of gate-all-around (GAA) Si nanowire (NW) field-effect transistors (FETs) operating in sub-22-nm CMOS technologies.
Journal ArticleDOI
Variability in Si Nanowire MOSFETs Due to the Combined Effect of Interface Roughness and Random Dopants: A Fully Three-Dimensional NEGF Simulation Study
TL;DR: In this article, the impact of surface roughness and its combination with random discrete dopants on the current variability in nanometer-scale nanowire metal-oxidesemiconductor field effect transistors was studied.
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Journal ArticleDOI
High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices
Navab Singh,Ajay Agarwal,Lakshmi Kanta Bera,Tsung-Yang Liow,R. Yang,S.C. Rustagi,C.H. Tung,Rakesh Kumar,G. Q. Lo,N. Balasubramanian,Dim-Lee Kwong +10 more
TL;DR: In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.