S
Selin H. G. Teo
Researcher at Agency for Science, Technology and Research
Publications - 28
Citations - 966
Selin H. G. Teo is an academic researcher from Agency for Science, Technology and Research. The author has contributed to research in topics: Silicon & Transistor. The author has an hindex of 14, co-authored 28 publications receiving 917 citations. Previous affiliations of Selin H. G. Teo include University of Washington & Nanyang Technological University.
Papers
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Journal ArticleDOI
Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET
TL;DR: In this paper, the authors presented a vertical gate-all-around silicon nanowire transistor on bulk silicon wafer utilizing fully CMOS compatible technology, which achieved high aspect ratio (up to 50: 1) vertical nanowires with diameter ~20 nm.
Journal ArticleDOI
Ultralow drive voltage silicon traveling-wave modulator
Tom Baehr-Jones,Ran Ding,Yang Liu,Ali Ayazi,Thierry Pinguet,Nicholas C. Harris,Matthew Streshinsky,Poshen Lee,Yi Zhang,Andy Eu-Jin Lim,Tsung-Yang Liow,Selin H. G. Teo,Guo-Qiang Lo,Michael Hochberg +13 more
TL;DR: A CMOS-compatible broadband traveling-wave modulator based on a reverse-biased pn junction is demonstrated, demonstrating operation with a drive voltage of 0.63 Vpp at 20 Gb/s, a significant improvement in the state of the art.
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CMOS Inverter Based on Gate-All-Around Silicon-Nanowire MOSFETs Fabricated Using Top-Down Approach
S.C. Rustagi,Navab Singh,Wei-Wei Fang,K.D. Buddharaju,S. R. Omampuliyur,Selin H. G. Teo,C.H. Tung,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +9 more
TL;DR: In this article, the integration of gate-all-around (GAA) Si-nanowire transistors into CMOS inverters using top-down approach is demonstrated, for the first time, and the results are discussed in light of the circuit performances reported for other advanced nonclassical device architectures such as FinFETs.
Journal ArticleDOI
Si-Nanowire Based Gate-All-Around Nonvolatile SONOS Memory Cell
J. Fu,Navab Singh,K.D. Buddharaju,Selin H. G. Teo,C. Shen,Y. Jiang,Chunxiang Zhu,Mingbin Yu,G. Q. Lo,N. Balasubramanian,Dim-Lee Kwong,Elena Gnani,Giorgio Baccarani +12 more
TL;DR: In this paper, a gate-all-around Si-nanowire (NW) nonvolatile memory cell is proposed for high-speed NAND-type non-volatile flash memory applications.
Posted Content
A 25 Gb/s Silicon Photonics Platform
Tom Baehr-Jones,Ran Ding,Ali Ayazi,Thierry Pinguet,Matthew Streshinsky,Nicholas C. Harris,Jing Li,Li He,Michael N. Gould,Yi Zhang,Andy Eu-Jin Lim,Tsung-Yang Liow,Selin H. G. Teo,Guo-Qiang Lo,Michael Hochberg +14 more
TL;DR: In this article, an optical-lithography, wafer-scale photonics platform with 25 Gb/s operation was demonstrated, with an ultra-low drive voltage of 1 Vpp at 25 GHz.