Scaling the Si MOSFET is reconsidered. Requirements on subthreshold leakage control force conventional scaling to use high doping as the device dimension penetrates into the deep-submicrometer regime, leading to an undesirably large junction capacitance and degraded mobility. By studying the scaling of fully depleted SOI devices, the important concept of controlling horizontal leakage through vertical structures is highlighted. Several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design. The concept of vertical doping engineering can also be realized in bulk Si to obtain good subthreshold characteristics without large junction capacitance or heavy channel doping. >

Scaling the Si MOSFET: from bulk to SOI to bulk

In an ever increasing need for higher current drive and better short-channel characteristics, silicon-on-insulator MOS transistors are evolving from classical, planar, single-gate devices into three-dimensional devices with multiple gates (double-, triple- or quadruple-gate devices). The evolution and the properties of such devices are described and the emergence of a new class of MOSFETs, called triple-plus (3 + )-gate devices offer a practical solution to the problem of the ultimate, yet manufacturable, silicon MOSFET.

Multiple-gate SOI MOSFETs

A formula is derived, which shows that the subthreshold swing of field-effect interband tunnel transistors is not limited to 60 mV/dec as in the MOSFET. This formula is consistent with two recent reports of interband tunnel transistors, which show lower than 60-mV/dec subthreshold swings and provides two simple design principles for configuring these transistors. One of these principles suggests placing the gate adjacent to the tunnel junction. Modeling of this configuration verifies that sub-60-mV/dec swing is possible.

Low-subthreshold-swing tunnel transistors

We present a scaling theory for fully-depleted, cylindrical MOSFET's. This theory was derived from the cylindrical form of Poisson's equation by assuming a parabolic potential in the radial direction. Numerical device simulation data for subthreshold slope and DIBL were compared to the model to validate the formula. By employing the scaling theory a comparison with double-gate (DG) MOSFET's was carried out illustrating an improvement of up to 40% in the minimum effective channel length for the cylindrical device.

Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's

A scaling theory for double-gate SOI MOSFETs, which gives guidance for device design (silicon thickness t/sub si/; gate oxide thickness t/sub ox/) that maintains a subthreshold factor for a given gate length is discussed. According to the theory, a device can be designed with a gate length of less than 0.1 mu m while maintaining the ideal subthreshold factor. This is verified numerically with a two-dimensional device simulator. >

Scaling theory for double-gate SOI MOSFET's

The short-channel effect in fully depleted silicon-on-insulator MOSFETs has been studied by a two-dimensional analytical model and by computer simulation. The calculated values agree well with the simulation results. It is found that the vertical field through the depleted film strongly influences the lateral field across the source and drain regions. The short-channel effect can be significantly reduced by decreasing the silicon film thickness. >

Short-channel effect in fully depleted SOI MOSFETs

The conduction characteristics of fully depleted SOI MOSFETs studied by theoretical analysis and computer simulation are discussed. In these devices the ideal inverse subthreshold slope of 59.6 mV/decade is obtained if the interface-state capacitances are much smaller than the gate-oxide and silicon-film capacitances. For above-threshold conduction, with decreasing silicon film thickness the inversion charges penetrate more deeply into the film and the transconductance increases because of the decreasing fraction of surface conduction. >

Analysis of conduction in fully depleted SOI MOSFETs

A proposed breakdown model includes the effects of floating substrate and finite silicon thickness. The calculated I-V characteristics in the breakdown region agree well with the experimental results. The results show that (1) the drain-source breakdown voltage of silicon-on-insulator (SOI) n-MOSFETs increases with increasing channel length, increasing positive substrate voltage, and decreasing silicon film thickness; and (2) SOI n-MOSFETs have higher breakdown voltage than their bulk-silicon counterparts at large gate bias, but lower breakdown voltage at small gate bias. >

Avalanche-induced drain-source breakdown in silicon-on-insulator n-MOSFETs

Two-dimensional numerical simulations indicate that a surface-potential bending greater than the Si-film Fermi potential is required to reach the threshold condition for the near-intrinsic thin-film SOI (silicon-on-insulator) MOSFETs. Additionally, both n- and p-type SOI films result in approximately the same device threshold voltage when in the near intrinsic state and fully depleted condition. The threshold voltages of these devices are mainly dependent on the work function of gate material. High-performance submicrometer near-intrinsic thin-film SOI complementary MOSFETs with balanced threshold voltages of about 0.4 V (negative for PMOSFETs) are achievable with proper selection of gate material and back-gate bias. For very thin (less than 100 nm) SOI films, drain-induced barrier lowering (DIBL) is not sufficient to cause degradation of the threshold voltage or punchthrough behavior in the submicrometer region. For relatively thick (greater than 100 nm) SOI films, DIBL becomes more pronounced but can be suppressed by a proper back-gate bias. The simulated front-gate linear transconductance remains nearly constant up to about 10/sup 15/ cm/sup -3/ and then falls off rapidly with increasing doping concentration because of mobility degradation. The subthreshold slope increases with decreasing drain voltage as a result of DIBL, but the increase is small for very thin SOI films. >

K.K. Young

Papers

Short-channel effect in fully depleted SOI MOSFETs

Analysis of conduction in fully depleted SOI MOSFETs

Avalanche-induced drain-source breakdown in silicon-on-insulator n-MOSFETs

Submicrometer near-intrinsic thin-film SOI complementary MOSFETs