J.A. Burns

TL;DR: In this paper, the authors describe the rationale and development of a wafer-scale three-dimensional (3D) integrated circuit technology and the essential elements of the 3D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision waferwafer alignment using an in-house developed alignment system, low-temperature wafer wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances.

TL;DR: In this article, a 1024/spl times/1024 integrated image sensor with 8 /spl mu/m pixels, developed with 3D fabrication in 150 mm wafer technology, is presented.

TL;DR: In this article, the feasibility of stacking SOI circuits to build 3D-ICs with dense vertical interconnects is discussed, and the results are applied to develop higher performance systems.

TL;DR: In this article, the authors proposed a breakdown model including the effects of floating substrate and finite silicon thickness, and calculated I-V characteristics in the breakdown region agree well with the experimental results, showing that the drain-source breakdown voltage of SOI n-MOSFETs increases with increasing channel length, increasing positive substrate voltage, and decreasing silicon film thickness.

TL;DR: A 64times64 laser-radar (ladar) detector array with 50mum pixel size measures the arrival times of single photons using Geiger-mode avalanche photodiodes (APD).