Machine Learning is the study of methods for programming computers to learn. Computers are applied to a wide range of tasks, and for most of these it is relatively easy for programmers to design and implement the necessary software. However, there are many tasks for which this is difficult or impossible. These can be divided into four general categories. First, there are problems for which there exist no human experts. For example, in modern automated manufacturing facilities, there is a need to predict machine failures before they occur by analyzing sensor readings. Because the machines are new, there are no human experts who can be interviewed by a programmer to provide the knowledge necessary to build a computer system. A machine learning system can study recorded data and subsequent machine failures and learn prediction rules. Second, there are problems where human experts exist, but where they are unable to explain their expertise. This is the case in many perceptual tasks, such as speech recognition, hand-writing recognition, and natural language understanding. Virtually all humans exhibit expert-level abilities on these tasks, but none of them can describe the detailed steps that they follow as they perform them. Fortunately, humans can provide machines with examples of the inputs and correct outputs for these tasks, so machine learning algorithms can learn to map the inputs to the outputs. Third, there are problems where phenomena are changing rapidly. In finance, for example, people would like to predict the future behavior of the stock market, of consumer purchases, or of exchange rates. These behaviors change frequently, so that even if a programmer could construct a good predictive computer program, it would need to be rewritten frequently. A learning program can relieve the programmer of this burden by constantly modifying and tuning a set of learned prediction rules. Fourth, there are applications that need to be customized for each computer user separately. Consider, for example, a program to filter unwanted electronic mail messages. Different users will need different filters. It is unreasonable to expect each user to program his or her own rules, and it is infeasible to provide every user with a software engineer to keep the rules up-to-date. A machine learning system can learn which mail messages the user rejects and maintain the filtering rules automatically. Machine learning addresses many of the same research questions as the fields of statistics, data mining, and psychology, but with differences of emphasis. Statistics focuses on understanding the phenomena that have generated the data, often with the goal of testing different hypotheses about those phenomena. Data mining seeks to find patterns in the data that are understandable by people. Psychological studies of human learning aspire to understand the mechanisms underlying the various learning behaviors exhibited by people (concept learning, skill acquisition, strategy change, etc.).

Machine learning

The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.

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A survey of research and practices of Network-on-chip

Massive multiple-input multiple-output MIMO is one of themost promising technologies for the next generation of wirelesscommunication networks because it has the potential to providegame-changing improvements in spectral efficiency SE and energyefficiency EE. This monograph summarizes many years ofresearch insights in a clear and self-contained way and providesthe reader with the necessary knowledge and mathematical toolsto carry out independent research in this area. Starting froma rigorous definition of Massive MIMO, the monograph coversthe important aspects of channel estimation, SE, EE, hardwareefficiency HE, and various practical deployment considerations.From the beginning, a very general, yet tractable, canonical systemmodel with spatial channel correlation is introduced. This modelis used to realistically assess the SE and EE, and is later extendedto also include the impact of hardware impairments. Owing tothis rigorous modeling approach, a lot of classic "wisdom" aboutMassive MIMO, based on too simplistic system models, is shownto be questionable.

https://www.nowpublishers.com/article/DownloadSummary/SIG-093

Massive MIMO Networks: Spectral, Energy, and Hardware Efficiency

Sustainable operation of battery powered wireless embedded systems (such as sensor nodes) is a key challenge, and considerable research effort has been devoted to energy optimization of such systems. Environmental energy harvesting, in particular solar based, has emerged as a viable technique to supplement battery supplies. However, designing an efficient solar harvesting system to realize the potential benefits of energy harvesting requires an in-depth understanding of several factors. For example, solar energy supply is highly time varying and may not always be sufficient to power the embedded system. Harvesting components, such as solar panels, and energy storage elements, such as batteries or ultracapacitors, have different voltage-current characteristics, which must be matched to each other as well as the energy requirements of the system to maximize harvesting efficiency. Further, battery nonidealities, such as self-discharge and round trip efficiency, directly affect energy usage and storage decisions. The ability of the system to modulate its power consumption by selectively deactivating its sub-components also impacts the overall power management architecture. This paper describes key issues and tradeoffs which arise in the design of solar energy harvesting, wireless embedded systems and presents the design, implementation, and performance evaluation of Heliomote, our prototype that addresses several of these issues. Experimental results demonstrate that Heliomote, which behaves as a plug-in to the Berkeley/Crossbow motes and autonomously manages energy harvesting and storage, enables near-perpetual, harvesting aware operation of the sensor node.

Design Considerations for Solar Energy Harvesting Wireless Embedded Systems

Using detailed traces from 255 users, we conduct a comprehensive study of smartphone use. We characterize intentional user activities -- interactions with the device and the applications used -- and the impact of those activities on network and energy usage. We find immense diversity among users. Along all aspects that we study, users differ by one or more orders of magnitude. For instance, the average number of interactions per day varies from 10 to 200, and the average amount of data received per day varies from 1 to 1000 MB. This level of diversity suggests that mechanisms to improve user experience or energy consumption will be more effective if they learn and adapt to user behavior. We find that qualitative similarities exist among users that facilitate the task of learning user behavior. For instance, the relative application popularity for can be modeled using an exponential distribution, with different distribution parameters for different users. We demonstrate the value of adapting to user behavior in the context of a mechanism to predict future energy drain. The 90th percentile error with adaptation is less than half compared to predictions based on average behavior across users.

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Diversity in smartphone usage

As an increasing number of electronic systems are powered by batteries, battery life becomes a primary design consideration. Maxiimizing battery life requires system designers to develop an understanding of the capabilities and limitations of the batteries that power such systems, and to incorporate battery considerations into the system design process. Recent research has shown that, the amount of energy that can be supplied by a given battery varies significantly, depending on how the energy is drawn. Consequently, researchers are attempting to develop new battery-driven approaches to system design, which deliver battery life improvements over and beyond what can be achieved through conventional low-power design techniques. This paper presents an introduction to this emerging area, surveys promising technologies that have been developed for battery modeling and battery-efficient system design, and outlines emerging industry standards for smart battery systems.

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Battery-Driven System Design: A New Frontier in Low Power Design

Since battery life directly impacts the extent and duration of mobility, one of the key considerations in the design of a mobile embedded system should be to maximize the energy delivered by the battery, and hence the battery lifetime. To facilitate exploration of alternative implementations for a mobile embedded system, in this paper we address the issue of developing a fast and accurate battery model, and providing a framework for battery life estimation of Hardware/Software (HW/SW) embedded systems. We introduce a stochastic model of a battery, which can simultaneously model two key phenomena affecting the battery life and the amount of energy that can be delivered by the battery: the rate capacity effect and the recovery effect. We model the battery behavior mathematically in terms of parameters that can be related to physical characteristics of the electro-chemical cell. We show how this model can be used for battery life estimation of a HW/SW embedded system, by calculating battery discharge demand waveforms using a power co-estimation technique. Based on the discharge demand, the battery model estimates the battery lifetime as well as the delivered energy. Application of the battery life estimation methodology to three system implementations of an example TCP/IP network interface subsystem demonstrates that different system architectures can have significantly different delivered energy and battery lifetimes.

Battery life estimation of mobile embedded systems

This paper presents a novel system-level performance analysis technique to support the design of custom communication architectures for system-on-chip integrated circuits. Our technique fills a gap in existing techniques for system-level performance analysis, which are either too slow to use in an iterative communication architecture design framework (e.g., simulation of the complete system) or are not accurate enough to drive the design of the communication architecture (e.g., techniques that perform a "static" analysis of the system performance). Our technique is based on a hybrid trace-based performance-analysis methodology in which an initial cosimulation of the system is performed with the communication described in an abstract manner (e.g., as events or abstract data transfers). An abstract set of traces are extracted from the initial cosimulation containing necessary and sufficient information about the computations and communications of the system components. The system designer then specifies a communication architecture by: 1) selecting a topology consisting of dedicated as well as shared communication channels (shared buses) interconnected by bridges; 2) mapping the abstract communications to paths in the communication architecture; and 3) customizing the protocol used for each channel. The traces extracted in the initial step are represented as a communication analysis graph (CAG) and an analysis of the CAG provides an estimate of the system performance as well as various statistics about the components and their communication. Experimental results indicate that our performance-analysis technique achieves accuracy comparable to complete system simulation (an average error of 1.88%) while being over two orders of magnitude faster.

System-level performance analysis for designing on-chip communication architectures

This paper presents Lotterybus, a novel high-performance communication architecture for system-on-chip (SoC) designs. The Lotterybus architecture was designed to address the following limitations of current communication architectures: (i) lack of control over the allocation of communication bandwidth to different system components or data flows (e.g., in static priority based shared buses), leading to starvation of lower priority components in some situations, and (ii) significant latencies resulting from variations in the time-profile of the communication requests (e.g., in time division multiplexed access (TDMA) based architectures), sometimes leading to larger latencies for high-priority communications.We present two variations of Lotterybus: the first is a low overhead architecture with statically configured parameters, while the second variant is a more sophisticated architecture, in which values of the architectural parameters are allowed to vary dynamically.Our experiments investigate the performance of the Lotterybus architecture across a wide range of communication traffic characteristics. In addition, we also analyze its performance in a 4x4 ATM switch sub-system design. The results demonstrate that the Lotterybus architecture is (i) capable of providing the designer with fine grained control over the bandwidth allocated to each SoC component or data flow, and (ii) well suited to provide high priority communication traffic with low latencies (we observed upto 85.4\% reduction in communication latencies over conventional on-chip communication architectures).

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LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs

Rapid growth in the complexity of system-on-chips is being accompanied by increasing volume and diversity of on-chip communication traffic, which in turn, is driving the development of advanced system-level communication architectures. While these architectures have the potential to improve system performance, they pose significant new challenges to the system designer, owing to the complex design space defined by the availability of numerous network topologies, communication protocols, and mapping alternatives for system communications. In this paper, we address the problem of mapping a system's communication requirements to a given communication architecture template. We illustrate the nature of the communication architecture design space, and describe an exploration methodology that uses efficient algorithms to help automate the process of mapping the system communications to the selected template. In addition, we demonstrate the importance of simultaneously optimizing the on-chip communication protocols in order to maximize system performance. Experiments conducted on example systems, including a cell forwarding unit of an ATM switch, indicate that the proposed techniques aid in automatically constructing communication architectures that have high performance. For the systems we considered, the solutions generated using our methodology had 53% superior performance (on average), over those based on conventional architectures and mapping approaches. The algorithms used in the proposed methodology are computationally efficient, and scale well with increasing communication architecture complexity.

/pdf/design-space-exploration-for-optimizing-on-chip-3yqe0wnnqd.pdf

K. Lahiri

Papers

Battery-Driven System Design: A New Frontier in Low Power Design

Battery life estimation of mobile embedded systems

System-level performance analysis for designing on-chip communication architectures

LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs

Design space exploration for optimizing on-chip communication architectures