The oxidation behaviour of metals and alloys at high temperatures in atmospheres containing water vapour: A review

We investigate the breakdown (V/sub br/) enhancement potential of the field plate (FP) technique in the context of AlGaN/GaN power HEMTs. A comprehensive account of the critical geometrical and material variables controlling the field distribution under the FP is provided. A systematic procedure is given for designing a FP device, using two-dimensional (2-D) simulation, to obtain the maximum V/sub br/, with minimum degradation in on-resistance and frequency response. It is found that significantly higher V/sub br/ can be achieved by raising the dielectric constant (/spl epsi//sub i/) of the insulator beneath the FP. Simulation gave the following estimates. The FP can improve the V/sub br/ by a factor of 2.8-5.1, depending on the 2-DEG concentration (n/sub s/) and /spl epsi//sub i/. For n/sub s/=1/spl times/10/sup 13//cm/sup 2/, the V/sub br/ can be raised from 123 V to 630 V, using a 2.2 /spl mu/m FP on a 0.8 /spl mu/m silicon nitride, and 4.7 /spl mu/m gate-drain separation. The methodology of this paper can be extended to the design of FP structures in other lateral FETs, such as MESFETs and LD-MOSFETs.

Enhancement of breakdown voltage in AlGaN/GaN high electron mobility transistors using a field plate

After defining the multiplication factor and the ionization rate together with their interrelationship, multiplication and breakdown models for diodes and MOS transistors are discussed. Different ionization models are compared and test structures are discussed for measuring the multiplication factor accurately enough for reliable extraction of the ionization rates. Multiplication measurements at different temperatures are performed on a bipolar NPN transistor, and yield new electron ionization rates at relatively low electrical fields. An explanation for the spread of the experimental values of the existing data on ionization rate is given. A new implementation method for a local avalanche model into a device simulator is presented. The results are less sensitive to the chosen grid size than the ones obtained from the existing method.

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Impact ionization in silicon: A review and update

Japanese journal of applied physics : JJAP online.

Over the past four decades, the field of silicon piezoresistive pressure sensors has undergone a major revolution in terms of design methodology and fabrication processes. Cutting edge fabrication technologies have resulted in improved precision in key factors like dimensions of diaphragm and placement of piezoresistors. Considering the unique nature of each sensor and the trade-offs in design, it is not feasible to follow a standard design approach. Thus, it is useful to derive the specific design from a number of important factors to arrive at the `ideal' design. In this paper, we critically review and analyze the various design considerations and principles for silicon piezoresistive pressure sensor. We also report the effect of these considerations on the sensor output taking help of various CAD tools. Keeping in view the accuracy of state-of-the-art fabrication tools and the stringent demands of the present day market, it has become important to include many of these design aspects. Modelling using analytical expressions for thin plates has also been looked into as it gives a quick guideline and estimation of critical parameters before detailed finite element method analysis. Wherever possible, fabrication imperfections and their effects have been discussed. Dependency of piezoresistive coefficients on temperature and doping concentration, the effect of clamping condition of diaphragms and fabrication using wet bulk micromachining is also analyzed. Silicon-on-insulator based sensors along with innovative design strategies, and future trends have also been discussed. This paper will serve as a quick and comprehensive guide for pressure sensor developers.

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Erratum to: Design principles and considerations for the `ideal' silicon piezoresistive pressure sensor: a focused review

In this paper, we show that when single gate SOI MOSFETs are biased at a particular ideal back gate voltage, the front and back channels can be turned ON and OFF simultaneously using the front gate voltage, thereby enhancing the current drive of the device. It is shown by analytical models as well as 2-D numerical simulation that both maximum transconductance and minimum subthreshold slope are obtained for this ideal back gate bias. Subsequently, n-channel and p-channel MOSFETs are designed for a conventional SOI CMOS process, where both the front and back channels of these devices turn ON and OFF simultaneously resulting in enhanced current drive and superior performance. The design has been carried out with the help of analytical formulation and verified using the 2-D Device Simulator MEDICI.

Design of single-gate n-channel and p-channel MOSFETs with enhanced current-drive due to simultaneous switching of front and back channels in SOI CMOS technology

The etching of single crystal silicon in ethylenediamine- pyrocatechol-water solutions (EDP) has been studied as a function of the composition of the etching solution. The solution with a constant composition of 7.5 ml of ethylenediamine (with 6g of pyrazine per liter) and 1.2g of pyrocatechol is used, and the water content is varied from 0 ml to 4 ml. Etch rate dependence on the active etching area is examined using three mask patterns having significantly different areas. It has been observed that etch rate depends significantly on the feature size in the solutions with higher water concentration and is almost independent of the area when the water content is 1 ml and below. Surface morphology was the other important criteria considered while optimizing the solution. Etch pit density (EPD) has been measured by etching the samples in different compositions to a constant depth of 45 micrometer. EPD is found to be high when the water content is above 2 ml and also when the amount of water is reduced below 0.5 ml. Minimal EPD is obtained when the water content is 0.5 ml. The optimized EDP solution containing 0.5 ml of water results in an etch rate of 44 micrometer/hr, independent of feature size and also good surface finish with EPD less than approximately 103/cm2.© (2001) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Optimization of EDP solutions for feature-size-independent silicon etching

In this paper the design, fabrication and testing of the capacitive micro accelerometer with Silicon On Insulator (SOI) approach is presented. The beam location with respect to a rectangular mass is optimized, using finite element analysis (FEM) to minimize cross axis sensitivity. It is demonstrated that a simple KOH etching with the addition of the tert-butanol can be easily adopted to fabricate the accelerometer structure without any convex undercutting effects. The devices are tested by electrostatic actuation.

Design optimization, fabrication and testing of a capacitive silicon accelerometer using an soi approach

In this paper, it is shown that Silicon-On-Insulator (SOI) wafers with good surface finish and thickness control can be realized using Silicon Fusion Bonding along with an optimized ethylenediamine-pyrocatechol-water (EDP) etching approach. Single crystal diaphragms of 11 μm thickness have been fabricated using these SOI wafers. These diaphragms were tested and found to withstand N2 gas pressures in excess of 260 psi without rupturing.

Silicon-on-insulator (SOI) wafer fabrication for MEMS applications

A combination of thermal SiO 2 and Plasma deposited SiN has been used as a dielectric film on silicon and the performance of these MNOS devices has been compared with MOS (Metal-Oxide-Silicon) and MNS (Metal-Nitride Silicon) structures. It has been observed that the MNOS devices have the best overall performance in terms of low Q f , D it , leakage current and high breakdown field strength and therefore is very attractive as an alternative dielectric for MOSFETs.

K.N. Bhat

Papers

Design of single-gate n-channel and p-channel MOSFETs with enhanced current-drive due to simultaneous switching of front and back channels in SOI CMOS technology

Optimization of EDP solutions for feature-size-independent silicon etching

Design optimization, fabrication and testing of a capacitive silicon accelerometer using an soi approach

Silicon-on-insulator (SOI) wafer fabrication for MEMS applications

Lower leakage and higher breakdown voltage for MNOS (Metal-Sin-SiO2-Si) structure