Showing papers in "Solid-state Electronics in 2006"
TL;DR: The paper reviews the physics underlying PCM operation, the scaling potentials of these devices and some options recently proposed for the cell structure and addresses the main challenges for the PCM to become fully competitive with standard Flash technology.
Abstract: Among the emerging non-volatile technologies, phase change memories (PCM) are the most attractive in terms of both performance and scalability perspectives. The paper reviews the physics underlying PCM operation, the scaling potentials of these devices and some options recently proposed for the cell structure. The paper also addresses the main challenges for the PCM to become fully competitive with standard Flash technology.
295 citations
TL;DR: In this article, the authors used indium gallium oxide transparent thin-film transistors (TTFTs) to construct high-frequency ring oscillators with a peak incremental mobility of ∼7 cm 2 ǫV −1 ǔ s −1 −1 and turn-on voltage of ∼2.2 V.
Abstract: Highly transparent ring oscillators, exhibiting ∼75% optical transmittance in the visible portion of the electromagnetic spectrum, are fabricated using indium gallium oxide as the active channel material and standard photolithography techniques. The n-channel indium gallium oxide transparent thin-film transistors (TTFTs) exhibit a peak incremental mobility of ∼7 cm 2 V −1 s −1 and turn-on voltage of ∼2 V. A five-stage ring oscillator circuit (which does not employ level-shifting) exhibits an oscillation frequency of ∼2.2 kHz when the gate and drain of the load transistor are biased at 30 V; the maximum oscillation frequency observed is ∼9.5 kHz, with the gate and drain of the load transistor biased at ∼80 V.
148 citations
TL;DR: In this article, the analysis of widening and narrowing of optical band gap in sol-gel derived ZnO films moderately doped with Yttrium and heavily doped sputtered znO film with aluminum and scandium was performed.
Abstract: In semiconductors, a widening of the optical band gap occurs because the lower states in the conduction band are blocked. At the same time band gap narrowing also occurs due to many body interactions on doping. This paper reports the analysis of widening and narrowing of optical band gap in sol–gel derived ZnO films moderately doped with Yttrium and heavily doped sputtered ZnO films with aluminum and scandium. The band gap was evaluated using optical transmission data. Carrier concentration was known from the Hall measurements. At high concentrations the effective change in band gap is found to be the difference of the band gap widening and band gap narrowing. At low concentration of dopant the many body theories do not apply and the experiments also show that the band gap narrowing is practically negligible at these concentrations and the effective band gap widening is determined by the band gap widening alone. The chemical nature of the dopant played practically no role.
127 citations
TL;DR: In this paper, a simple and successful method for evaluating the series resistance, the ideality factor, the saturation current and the shunt conductance in illuminated solar cells is presented, which involves the use of an auxiliary function and a computer-fitting routine.
Abstract: This paper presents a simple and successful method for evaluating the series resistance, the ideality factor, the saturation current and the shunt conductance in illuminated solar cells. The approach involves the use of an auxiliary function and a computer-fitting routine. The validity of this method has been confirmed by the way of current–voltage measurements of a commercial silicon solar cell, a module and a plastic solar cell.
123 citations
TL;DR: In this paper, the conduction band structure of silicon nanowires, its dependence with the wire width and its influences on the electrical performances of Si nanowire-based MOSFETs working in the ballistic regime were investigated.
Abstract: This work investigates the conduction band structure of silicon nanowires, its dependence with the wire width and its influences on the electrical performances of Si nanowire-based MOSFET’s working in the ballistic regime. The energy dispersions relations for Si nanowires have been calculated using a sp 3 tight-binding model and the ballistic response of n-channel devices with a 3D Poisson–Schrodinger solver considering a mode-space approach and open boundary conditions (NEGF formalism). Results are compared with data obtained considering the parabolic bulk effective mass approximation, highlighting in this last case the overestimation of the I on current, up to 60% for the smallest (1.36 nm × 1.36 nm Si wire) devices.
112 citations
TL;DR: In this article, the DC characteristics of AlGaN/GaN HFETs on Si substrates were reported as a function of temperature and gate length, and stable operation up to 500°C was obtained with no significant permanent degradation.
Abstract: The DC characteristics of AlGaN/GaN HFETs on Si substrates are reported as a function of temperature and gate length. Stable operation up to 500 °C was obtained with no significant permanent degradation. The temperature dependence of the saturation current was found to follow a power law of T−1.5 for long channel devices, but improved to show only a weak T−0.5 dependence for submicron gate length devices.
102 citations
TL;DR: In this article, the potential successors of the silicon CMOS technology at the end of the ITRS Roadmap (in ∼15 years) are discussed, and the disruptive technologies, rooted in nanoscale science, would aid in the continued advancement of integrated circuit technology.
Abstract: Future miniaturized devices, beyond the Moore’s law era of silicon, are expected to rely on new, ingenious methods to implement spatially controlled and highly functional nanoscale components synthesized by inexpensive chemistry. Chip technology based on self-assembly would enhance performance and packing density by orders of magnitude, deliver rich on-chip functionality, and operate at molecular level. Low-dimensional semiconductor nanostructues and organic molecules, which offer unique possibilities such as extremely low power dissipation, quantum effects, surface sensitivity and low synthesis cost, could be the building blocks for next-generation electronics. In this paper we discuss the potential successors of the silicon CMOS technology at the end of the ITRS Roadmap (in ∼15 years). The disruptive technologies, rooted in nanoscale science, would aid in the continued advancement of integrated circuit technology – not necessarily through straightforward transistor geometry scaling – in several mainstream applications such as computing and data storage.
97 citations
TL;DR: In this article, the scaling properties of TFETs were investigated using standard 130nm, 90nm, and 65nm CMOS process flows. But the TFET dependence on the design parameters, i.e. channel width and length, is comparable to that of the standard MOSFET.
Abstract: The scaling properties of the tunneling field effect transistor (TFET) are shown using standard 130 nm, 90 nm, and 65 nm CMOS process flows. For the different technology nodes the temperature dependence is presented. The device characteristic does not show degradation after a combined voltage and temperature cycle. It is shown that the TFET dependence on the design parameters, i.e. channel width and length, is comparable to that of the standard MOSFET. Experimental and simulation results are presented for mixed MOSFET/TFET circuits. The usage of the TFET does not cause delay degradation. The static power consumption and signal integrity are improved compared to the CMOS realization.
91 citations
TL;DR: The perovskite structure ZnSnO3 was prepared by hydrothermal process directly and its crystal structure and ceramic microstructure were characterized by X-ray diffraction (XRD) and transmission electron microscopy (TEM) as mentioned in this paper.
Abstract: The paper reports the preparation and gas sensing characteristic of ZnSnO3. The perovskite structure ZnSnO3 was prepared by hydrothermal process directly. Its crystal structure and ceramic microstructure were characterized by X-ray diffraction (XRD) and transmission electron microscopy (TEM) and scanning electron microscopy (SEM). Its grain size is about 500 nm, and homogeneous as well as monodispersive in shape. Furthermore, the gas sensing properties of the materials were tested in static state. It is found that the sensors have good sensitivity and selectivity to H2S.
90 citations
TL;DR: In this paper, the performance of TFT structures with zinc tin oxide channel layer was investigated and the channel mobility and turn-on voltage were extracted from measured electrical characteristics, thus mapping TFT performance (for the process and structure used here) across the zinc tin dioxide composition/processing temperature space.
Abstract: Thin-film transistor (TFT) structures with zinc tin oxide channel layer are fabricated and electrically characterized; zinc tin oxide composition (Zn:Sn ratio) and post-deposition anneal temperature are varied so as to explore their effects on electrical performance. Channel mobility and turn-on voltage are extracted from measured electrical characteristics, thus mapping TFT performance (for the process and structure used here) across the zinc tin oxide composition/processing temperature space. In general, mobility reaches a broad peak for intermediate compositions and anneal temperatures, while turn-on voltage decreases (becomes increasingly negative) with increasing anneal temperature and decreasing Zn:Sn ratio. These results comprise key information in assessing the potential of zinc tin oxide as a candidate TFT channel layer material.
87 citations
TL;DR: In this paper, the fabrication of AlGaN/GaN high electron mobility transistor (HEMT) with high breakdown voltage by employing the metal insulator-semiconductor (MIS) gate structure was reported.
Abstract: We report the fabrication of AlGaN/GaN high electron mobility transistor (HEMT) with high breakdown voltage by employing the metal-insulator-semiconductor (MIS) gate structure. SiO2, SiN, and TiO2 were used for the insulators. The gate leak current was significantly reduced by employing the MIS structure, and the breakdown voltage characteristics were improved. The breakdown voltage of the MIS–HEMTs increased non-linearly with the increase of gate-drain length Lgd. The TiO2 insulator exhibited highest breakdown voltage of 2 kV with the on-resistance of 15.6 mΩ cm2 for Lgd = 28 μm. On the other hand, the breakdown voltage and on-resistance for SiN MIS–HEMT were found to be 1.7 kV and 6.9 mΩ cm2, respectively. We demonstrated that AlGaN/GaN MIS–HEMTs are promising not only for high speed applications but also for high power switching applications.
TL;DR: In this article, a continuous compact model for the drain current, including short-channel effects and carrier quantization in Double-Gate MOSFETs, is developed, particularly well-adapted to ultra-scaled devices, with short channel lengths and ultra-thin silicon films.
Abstract: A continuous compact model for the drain current, including short-channel effects and carrier quantization in Double-Gate MOSFET is developed. The model is particularly well-adapted to ultra-scaled devices, with short channel lengths and ultra-thin silicon films. An extensive comparison step with 2D quantum numerical results fully validates the model. The model is also shown to reproduce with an excellent accuracy experimental drain current in Double-Gate devices. Finally, the drain current model has been supplemented by a node charge model and the resulting DG model has been successfully implemented in Eldo IC analog simulator, demonstrating the application of the model to circuit simulation.
TL;DR: In this paper, the authors investigated the charge and discharge phenomena of Germanium nanocrystals fabricated by low pressure chemical vapor deposition, by means of Capacitance-Voltage and capacitance decay measurements.
Abstract: Charge and discharge phenomena of Germanium nanocrystals fabricated by low pressure chemical vapor deposition are investigated by means of Capacitance–Voltage and capacitance decay measurements. The study shows fast programming and erasing times as compared with conventional devices. It is shown that the charge saturation depends on the gate voltage stress in the low electric field regime. For high gate voltages, a saturation of the stored charge is obtained, indicating that the density of trapped carriers in Ge nanocrystals is limited and depends only on the dots size. Capacitance decay measurements exhibits a very long retention time for holes as compared with silicon nanocrystal memories. This is mainly due to the barrier height for holes at the nc-Ge/ 2 interface. A model for simulation of the retention kinetics has been developed and allows to extract the band alignment of the nc-Ge/SiO 2 /Si system. The simulation results are then used to determine the band gap energy of Ge nanocrystals. Finally, it is shown that Ge nanocrystals are very good candidates for P-type Metal Oxide Semiconductor nonvolatile memories.
TL;DR: In this paper, the first principles full-potential linearized augmented plane wave calculations (FP-LAPW) with density functional theory in local density approximations (LDA) were performed to determine and to predict the pressure dependence of structural and optical properties of zinc-blende BeS, BeSe and BeTe compounds.
Abstract: We have performed the first principles full-potential linearized augmented plane wave calculations (FP-LAPW) with density functional theory in local density approximations (LDA), in aim to determine and to predict the pressure dependence of structural and optical properties of zinc-blende BeS, BeSe and BeTe compounds. The elastic constant, refractive index and its variation with hydrostatic pressure are well described.
TL;DR: In this article, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs is proposed.
Abstract: In this paper, we propose for the first time, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs. The impact of (i) lateral source/drain doping gradient ( d ), (ii) spacer width ( s ), (iii) spacer to doping gradient ratio ( s / d ) and (iv) silicon film thickness ( T si ), on short channel effects – threshold voltage ( V th ) and subthreshold slope ( S ), on-current ( I on ), off-current ( I off ) and I on / I off is extensively analysed by using the analytical model and 2D device simulations. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients and effective channel lengths. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimised to achieve high values of on-currents. The present work provides valuable design insights in the performance of nanoscale DG SOI devices with optimal source/drain engineering and serves as a tool to optimise important device and technological parameters for 65 nm technology node and below.
TL;DR: In this paper, the authors report on the determination of accurate equivalent circuit models from scattering parameter measurements of this novel kind of transistor, since it is an essential step to make a straightforward and physical consistent investigation of the RF behaviour.
Abstract: In the last few years, the fin field effect transistor is emerging as leading structure to continue the scaling of CMOS technology into nanometer regime. Here, we report on the determination of accurate equivalent circuit models from scattering parameter measurements of this novel kind of transistor, since it is an essential step to make a straightforward and physical consistent investigation of the RF behaviour. We focused on the bias dependence and the scalability of the extracted small signal model parameters. It is found that the extracted equivalent circuit parameters of the interdigitated multiple fin transistors under test follow successfully the conventional straightforward scaling rules and their bias dependence is in line with the expectations.
TL;DR: In this article, structural and electronic parameters of zincblende GaAs are obtained from density-functional-theory calculations utilizing an ab initio total energy pseudopotential technique within the local density and the generalized gradient approximations.
Abstract: Structural and electronic parameters of zincblende GaAs are obtained from density-functional-theory calculations utilizing an ab initio total energy pseudopotential technique within the local-density and the generalized gradient approximations. Detailed comparisons are made with the existing measured values and with results obtained in previous theoretical studies. The agreement between the present results and the available data from the literature is roughly satisfactory. Dependencies of some computed quantities on pressure are examined.
TL;DR: In this paper, the authors presented a semi-empirical analytic closed-form charge-based expression for the drain current of asymmetric DG MOSFETs that is valid from weak to strong inversion and retains the asymptotic behavior.
Abstract: Although both exact [Taur Y, Liang X, Wang W, Lu H. A continuous, analytic drain-current model for DG MOSFETs. IEEE Electron Dev Lett 2004;25(2):399–401] and design oriented approximate [Sallese JM, Krummenacher F, Prgaldiny F, Lallement C, Roy A, Enz C. A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism. Solid-State Electron 2005;49(3):485–9] closed-form analytical solution of the drain current for the symmetric double gate (DG) MOST exist, a closed-form expression for asymmetric DG MOST is still lacking. In this context, this work presents a semi-empirical analytic closed-form charge-based expression for the drain current of asymmetric DG MOST that is valid from weak to strong inversion and retains the asymptotic behavior. In addition, important small-signal quantities such as the transconductance-to-current ratio are readily obtained and reveal that these are nearly insensitive to the degree of asymmetry.
TL;DR: In this paper, the intersecting behavior of I-V curves measured at different temperatures for inhomogeneous Schottky diodes with a common series resistance was studied and an analytical expression for the voltage where I-T curves have their minima and the existence of which is a necessary condition for the intersection of I−V curves was derived.
Abstract: We have studied intersecting behaviour of I–V curves measured at different temperatures for inhomogeneous Schottky diodes with a common series resistance. Analytical expression for the voltage where I–T curves have their minima and the existence of which is a necessary condition for the intersection of I–V curves was derived. It is shown that this voltage remains in the low voltage region where I–V curves of Schottky diodes are commonly measured.
TL;DR: In this article, a carrier-based analytic DCIV model for the long channel undoped cylindrical surrounding-gate MOSFETs is presented based on an exact solution of the Poisson equation and a Pao-Sah current formulation in terms of the carrier concentration.
Abstract: A carrier-based analytic DCIV model for the long channel undoped cylindrical surrounding-gate MOSFETs is presented in this paper. It is based on an exact solution of the Poisson equation and a Pao–Sah current formulation in terms of the carrier concentration. From this model, the different dependences of the surface potential, centric potential, inversion charge and the current on the silicon body thickness and the gate oxide are elucidated analytically and then the predicted DCIV characteristics are compared with the 3D numerical simulations. The analytical results of the model presented also show in a good agreement with the 3D simulation, demonstrating the model is valid for all operation regions and traces the transition between them without any need for the fitting parameter.
TL;DR: In this paper, a new model is presented for DG SOI and single-gate SOI DC, RF and noise modelling, which is based on the active line approach and the concept of linear noise theory of two ports for calculating the macroscopic noise sources.
Abstract: Double gate fully depleted silicon-on-insulator (DG SOI) is recognized as a possible solution when physical length reduces to nanoscale. In this paper, a new model is presented for DG SOI and single gate SOI (SG SOI) DC, RF and noise modelling. Using this model, the SG SOI and DG SOI analog and noise performance are compared. We have developed for such purpose a noise modeling based on the active line approach and the concept of linear noise theory of two ports for calculating the macroscopic noise sources. The channel is split into elemental sections constituted of a local small signal equivalent circuit associated to an additional microscopic diffusion noise source. DC tunneling gate current expression was implemented.
TL;DR: In this article, a general purpose numerical Schrodinger-Poisson solver for radially symmetric nanowire core-shell structures for electronic and optoelectronic applications is presented.
Abstract: We present here a general purpose numerical Schrodinger–Poisson solver for radially symmetric nanowire core–shell structures for electronic and optoelectronic applications. The solver provides self-consistent solutions of the Schrodinger equation and the Poisson equation in cylindrical coordinates, for nanowire core–shell structures with radial compositional variation. Quantized energy levels as well as their associated electron wavefunctions and populations can be obtained from the solutions. Individual equation solvers were verified by comparison with scenarios where analytical results exist; verification of the self-consistent solution process was done by comparing results in the large radius limit with numerical solutions for a rectangular slab structure. We apply this solver to compute the charge/capacitance–voltage characteristics for a nanowire field effect device with wrap-around gate. It is shown that quantum confinement and the low dimensionality can give rise to, for representative nanowire FETs considered, ∼30% reduction in gate capacitance compared to the classically predicted value, and is ∼1/3 of the geometrical barrier limited capacitance.
TL;DR: In this paper, a H 2 S sensor formed from hybrid of WO 3 and polypyrrole (PPy) by mechanical mixing was produced, and the gas-sensing properties of the hybrid materials were studied and compared with those of pure PPy and WO3.
Abstract: In this work, a H 2 S sensor formed from hybrid of WO 3 and polypyrrole (PPy) by mechanical mixing was produced. The gas-sensing properties of the hybrid materials were studied and compared with those of PPy and WO 3 . It was found that PPy/WO 3 materials can complement the drawbacks of pure PPy and WO 3 to some extent. PPy/WO 3 materials with varies PPy mass percent (1%, 3%, 5%, 10%, 20%) had better reversibility than PPy, and also had higher sensitivity than WO 3 when operated at 90 °C. The sensing mechanism of PPy/WO 3 materials to H 2 S was presumed to be the synergism of PPy and WO 3 or the effect of p–n heterojunctions.
TL;DR: In this paper, the reverse breakdown voltages (VB) as high as 630 V and 600 V were achieved for 50μm and 150μm diameter rectifiers, respectively.
Abstract: Vertical Schottky rectifiers have been fabricated on a free-standing n-GaN substrate. Circular Pt Schottky contacts with different diameters (50 μm, 150 μm and 300 μm) were prepared on the Ga-face and full backside ohmic contact was prepared on the N-face by using Ti/Al. The electron concentration of the substrate was as low as ∼7 × 1015 cm−3. Without epitaxial layer and edge termination scheme, the reverse breakdown voltages (VB) as high as 630 V and 600 V were achieved for 50 μm and 150 μm diameter rectifiers, respectively. For larger diameter (300 μm) rectifiers, VB dropped to 260 V. The forward turn-on voltage (VF) for the 50 μm diameter rectifiers was 1.2 V at the current density of 100 A/cm2, and the on-state resistance (Ron) was 2.2 mΩ cm2, producing a figure-of-merit (VB)2/Ron of 180 MW cm−2. At 10 V bias, forward currents of 0.5 A and 0.8 A were obtained for 150 μm and 300 μm diameter rectifiers, respectively. The devices exhibited an ultrafast reverse recovery characteristics, with the reverse recovery time shorter than 20 ns.
TL;DR: This model includes physical effects like the quasi-saturation, impact-ionization and self-heating, and a new general model for drift resistance, which can be used for any high voltage MOSFET with extended drift region.
Abstract: In this work, we present for the first time, a highly scalable general high voltage MOSFET model, which can be used for any high voltage MOSFET with extended drift region. This model includes physical effects like the quasi-saturation, impact-ionization and self-heating, and a new general model for drift resistance. The model is validated on the measured characteristics of two widely used high voltage devices in the industry i.e. LDMOS and VDMOS devices, and implemented on commercial circuit simulators like SABER (Synopsys), ELDO (Mentor Graphics), Spectre (Cadence) and UltraSim (Cadence). The accuracy of the model is better than 10% for DC I–V and g–V characteristics and shows good behavior for all capacitances which are unique for these devices showing peaks and shift of peaks with bias variation. The model also exhibits excellent scalability with transistor width, drift length, number of fingers and temperature.
TL;DR: In this article, the electrostatics of fully depleted cylindrical silicon-nanowire (SiCNW) FETs, 4G RNW-FETs and gate-all-around carbon-nanotube (GAA-CNT) CNTs at advanced miniaturization limits were investigated.
Abstract: In this work we investigate and compare the electrostatics of fully depleted cylindrical silicon-nanowire (SiCNW) FETs, four-gate rectangular nanowire (4G RNW) FETs, tri-gate rectangular nanowire (3G RNW) FETs and gate-all-around carbon-nanotube (GAA-CNT) FETs at advanced miniaturization limits. In doing so, we rigorously solve the coupled Schrodinger–Poisson equations within the device cross-sections and fully account for quantum-mechanical effects. The investigation, carried out for the 65 and 45 nm technology nodes, leads to the unexpected conclusion that, for an assigned threshold voltage, the gate-all-around CNT-FET offers only a slightly better performance with respect to the SiCNW and the 4G RNW-FETs. This is due to the compensation of two different mechanisms, namely a higher gate effectiveness and a lower density of states. The 3G RNW yields instead an electron density within the channel which is about 25% lower than the SiCNW and 4G RNW-FETs at a given gate voltage. Such a reduced performance is due to its inherent asymmetry, which negatively affects the gate control on the channel charge.
TL;DR: In this article, a vertical metaloxide-semiconductor field effect transistor (MOSFET) with a dielectric pocket between the channel and source/drain has been fabricated and tested.
Abstract: A vertical metal-oxide-semiconductor field-effect transistor with the novel feature of a dielectric pocket between the channel and source/drain has been fabricated and tested. These dielectric pocket vertical MOSFETs (DPV-MOSFETs) show an improved suppression of short-channel effects such as VT roll-off and drain induced barrier lowering (DIBL). This is due to reduced charge sharing, thus allowing better threshold voltage control. The dielectric pocket also prevents dopant diffusion from the source/drains into the body during device fabrication, mitigating bulk punchthrough.
TL;DR: In this paper, a simple preparation method of this organic memory material, compatible with industrial processing and downsizing of the memory cells, was presented, which achieved ON/OFF current ratio of about 100.
Abstract: CuTCNQ is an organic semiconductor charge transfer material that allows the realization of non-volatile cross-bar memory arrays with conductivity switching. In this work, we present a simple preparation method of this organic memory material, compatible with industrial processing and downsizing of the memory cells. CuTCNQ nanowires were prepared on Cu by a solid–gas phase corrosion reaction between the metal and hot TCNQ gas at low pressure. Surface coverage increased with reaction time and temperature. Cu/CuTCNQ/Al cross-point cell arrays with memory areas of 0.01 mm 2 exhibited I – V curves with ON/OFF current ratios of about 10. Further downscaling of the CuTCNQ nanowire memory elements was successful on top of 0.25 μm 2 copper-filled vias. Corresponding memories achieved ON/OFF current ratio of about 100. This is, to our knowledge, the first report on downscaling of organic memories to this size.
Abstract: In this paper, the analogue performance of a 65 nm node double gate SOI (DGSOI) is qualitatively investigated using MixedMode simulation. The intrinsic resistance of the device is optimised by evaluating the impact of the source/drain engineering using variation of spacers and doping profile on the RF key figures of merit such as fT, and fMAX. It is evident that longer spacers, which approach the length of the gate offer better RF performance irrespective of the profile as long as the doping gradient at the gate edge is
TL;DR: In this paper, a planar double-gate SOI MOSFET with gate length equal to 25nm is compared using device Monte Carlo simulation, and the tradeoff between access resistance and fringe capacitance is analyzed.
Abstract: Multiple-gate SOI MOSFETs with gate length equal to 25 nm are compared using device Monte Carlo simulation. In such architectures, the short channel effects may be controlled with much less stringent body and oxide thickness requirements than in single-gate MOSFET. Our results highlight that planar double-gate MOSFET is a good candidate to obtain high current drive per unit-width and low subthreshold leakage with aggressive delay time. Additionally, this device offers much better ability to high integration density than nonplanar devices as triple-gate or quadruple-gate MOSFETs. However, we show that source–drain regions have to be carefully scaled to optimize the trade off between access resistance and fringe capacitance.