A spectral conversion device including a plurality of discrete units dyed with a photoluminescent material at a concentration greater than or equal to an amount sufficient to absorb and convert substantially all input light from a light source to a desired output spectrum, and a coating material disposed around the discrete units, wherein the coating material binds the plurality of discrete units to form a matrix, wherein when the plurality of discrete units are positioned over the light source, the input light passing through the transparent discrete units is not converted, and the input light passing through the doped discrete units is converted to red and green wavelengths, further wherein the emitted input light and the converted red and green light correspond to the desired output spectrum to produce one or more colors. An associated method and an associated device used with flat panel image displays are also provided.

High efficiency and long life optical spectrum conversion device and process

3-D integrated circuits promise high bandwidth, low latency, low device power, and a small form factor. Increased device density and asymmetrical packaging, however, renders the design of 3-D power delivery a challenge. We investigate in this paper various methods to improve 3-D power delivery. We analyze the impact of through-silicon via (TSV) size and spacing, of controlled collapse chip connection (C4) spacing, and of dedicated power delivery TSVs. In addition to considering typical cylindrical or square metal-filled TSVs (core TSVs), we also investigate using coaxial TSVs for power delivery resulting in reduced routing blockages and added coupling capacitance. Our 3-D evaluation system is composed of a quad-core chip multiprocessor, a memory die, and an accelerator engine, and it is evaluated using representative SPEC benchmark traces. This is the first detailed architectural-level analysis for 3-D power delivery. Our findings provide clear guidelines for 3-D power delivery design. More importantly, we show that it is possible to achieve 2-D-like, or even better, power quality by increasing C4 granularity and by selecting suitable TSV size and spacing.

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Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies

3-D technology provides many benefits including high density, high bandwidth, low-power, and small form-factor. Through Silicon Via (TSV), which provides communication links for dies in vertical direction, is a critical design issue in 3-D integration. Just like other components, the fabrication and bonding of TSVs can fail. A failed TSV can severely increase the cost and decrease the yield as the number of dies to be stacked increases. A redundant TSV architecture with reasonable cost is proposed in this paper. Based on probabilistic models, some interesting findings are reported. First, the number of failed TSVs in a tier is usually less than 2 when the number of TSVs in a tier is less than 1000 and less than 5 when the number of TSVs in a tier is less than 10000. Assuming that there are at most 2-5 failed TSVs in a tier. With one redundant TSV allocated to one TSV block, our proposed structure leads to 90% and 95% recovery rates for TSV blocks of size 50 and 25, respectively. Finally, analysis on overall yield shows that the proposed design can successfully recover most of the failed chips and increase the yield of TSV to 99.4%.

TSV Redundancy: Architecture and Design Issues in 3-D IC

An illumination system generating light having at least one wavelength within 200 nm a plurality of nano-sized structures (e.g., voids). The optical fiber coupled to the light source. The light diffusing optical fiber has a core and a cladding. The plurality of nano-sized structures is situated either within said core or at a core-cladding boundary. The optical fiber also includes an outer surface. The optical fiber is configured to scatter guided light via the nano-sized structures away from the core and through the outer surface, to form a light-source fiber portion having a length that emits substantially uniform radiation over its length, said fiber having a scattering-induced attenuation greater than 50 dB/km for the wavelength(s) within 200 nm to 2000 nm range.

Optical fiber illumination systems and methods

LED based lamps and bulbs are disclosed that comprise a pedestal having a plurality of LEDs, wherein the pedestal at least partially comprises a thermally conductive material. A heat sink structure is included with the pedestal thermally coupled to the heat sink structure. A remote phosphor is arranged in relation to the LEDs so that at least some light from the LEDs passes through the remote phosphor and is converted to a different wavelength of light. Some lamp or bulb embodiments can emit a white light combination of light from the LEDs and the remote phosphor. These can include LEDs emitting blue light with the remote phosphor having a material that absorbs blue light and emits yellow or green light. A diffuser can be included to diffuse the emitting light into the desired pattern, such as omnidirectional.

Led based pedestal-type lighting structure

In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise problem, already a major issue in 2D, is even more severe in 3D. CMOS decoupling capacitors (decaps) have been used effectively for controlling power grid noise in the past, but with technology scaling, they have grown increasingly leaky. As an alternative, metal-insulator-metal (MIM) decaps, with high capacitance densities and low leakage current densities, have been proposed. In this paper, we explore the tradeoffs between using MIM decaps and traditional CMOS decaps, and propose a congestion-aware 3D power supply network optimization algorithm to optimize this tradeoff. The algorithm applies a sequence-of-linear-programs based method to find the optimum tradeoff between MIM and CMOS decaps. Experimental results show that power grid noise can be more effectively optimized after the introduction of MIM decaps, with lower leakage power and little increase in the routing congestion, as compared to a solution using CMOS decaps only.

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Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors

This article studies one of the EDA problems for 3D IC design. The article presents a design automation solution for power grid optimization in 3D ICs. The authors propose a congestion-aware 3D power supply network optimization algorithm, which applies a sequence-of-linear-programs-based method to optimize the power grid design. We explore the trade-offs between MIM decaps and traditional CMOS decaps in chip design, and we propose a congestion-aware 3D power supply network optimization algorithm to optimize this trade-off. One of the novel features of our work is that it optimizes the power supply network using both conventional CMOS decaps and metal insulator-metal (MIM) decaps. However, because MIM decaps are built between layers of metal interconnects, they present routing blockages to nets that attempt to cross them, and therein lies the trade-off. The properties of MIM decaps make them attractive for both 2D and 3D chips, but we pay particular attention to the 3D decap problem in this article because, first, the power integrity problem is particularly critical in 3D, and requires novel approaches that leverage advances in materials, and second, the added complexity of handling routing blockages in a constrained environment makes the 3D problem especially challenging.

Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity

A method of manufacturing a multicolored illuminator is disclosed. In an embodiment, a first transparent sheet (499) comprising light diffusing particles is provided. Second and third transparent cladding sheets (404) are provided on either sides of the first transparent sheet. A mirror (406) is provided adjacent to the second sheet. The first sheet, second sheet, third sheet and mirror are merged to give a multicolored illuminator.

Method of Manufacturing Multicolored Illuminator

A photo luminescent light source is disclosed. In one embodiment, the apparatus comprises a light conducting medium. This light conducting medium includes particles of photoluminescent material, and a light source placed along an edge of it. The photoluminescent material absorbs light generated by the light source, and emanates light of the wavelength characterized by the photoluminescence properties of particles. The distribution of light emitting photoluminescent particles is varied throughout the medium to emanate a predetermined light pattern. In another embodiment, the light source emits light of multiple colors. In yet another embodiment, the light source emits polarized light.

Photoluminescent light source

A multicolored linear light source is disclosed. In an embodiment the multicolored linear light source (100) comprises a linear light source (100) emanating light of a first spectrum, and regions of photoluminescent material (102,104,106). The light of the first spectrum interacts with regions of photoluminescent material (102,104,106) to give light of a different spectrum. The composition of different regions of photoluminescent material is different, providing light of different spectra in different regions.

Karthikk Sridharan

Papers

Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors

Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity

Method of Manufacturing Multicolored Illuminator

Photoluminescent light source

Multicolored Linear Light Source