K
Kazuhiro Komori
Researcher at Hitachi
Publications - 32
Citations - 782
Kazuhiro Komori is an academic researcher from Hitachi. The author has contributed to research in topics: EPROM & Transistor. The author has an hindex of 13, co-authored 32 publications receiving 782 citations. Previous affiliations of Kazuhiro Komori include Renesas Electronics.
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Patent
Semiconductor integrated circuit and nonvolatile memory element
TL;DR: In this article, a semiconductor integrated circuit device is provided on a polycrystalline substrate, and includes a plurality of word lines, data lines, and an electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of words and data lines.
Patent
Semiconductor device of an LDD structure having a floating gate
TL;DR: In this paper, a semiconductor integrated circuit device is provided which includes first field effect transistors of an LDD structure having a floating gate as memory cells and second field effect transistor as elements other than the memory cells.
Proceedings ArticleDOI
A flash-erase EEPROM cell with an asymmetric source and drain structure
Hitoshi Kume,Hiroshi Yamamoto,Tetsuo Adachi,T. Hagiwara,Kazuhiro Komori,T. Nishimoto,Atsuyoshi Koike,Satoshi Meguro,Tetsuya Hayashida,Toshihisa Tsukada +9 more
TL;DR: A flash-erase EEPROM cell which consists of a single floating gate transistor is described, based on self-aligned double polysilicon stacked gate structure without a select transistor, which enables an erasing time of less than one millisecond, Endurance and data retention characteristics is adequate for implementation in memory chips.
Patent
Method of making semiconductor device with memory cells and peripheral transistors
TL;DR: In this paper, the first field effect transistors of an LDD structure having a floating gate as memory cells were used as EPROMs, and the second FET transistors as elements other than the memory cells.
Patent
Non-volatile semiconductor memory device erasing operation
Hitoshi Kume,Yoshiaki Kamigaki,Tetsuo Adachi,Toshihisa Tsukada,Kazuhiro Komori,Toshiaki Nishimoto,Tadashi Muto,Toshiko Koizumi +7 more
TL;DR: In this paper, a tunnel erasing device for a nonvolatile semiconductor memory device comprising a source region and a drain region, a floating gate electrode having a part superposed on at least one of them through a gate insulating layer, and a control gate electrode disposed over the floating gate through an interlayer insulator layer, is described.