Time-to-digital converters (TDCs) are vital components in time and distance measurement and frequency-locking applications. There are many architectures for implementing TDCs, from simple counter TDCs to hybrid multi-level TDCs, which use many techniques in tandem. This article completes the review literature of TDCs by describing new architectures along with their benefits and tradeoffs, as well as the terminology and performance metrics that must be considered when choosing a TDC. It describes their implementation from the gate level upward and how it is affected by the fabric of the device [field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC)] and suggests suitable use cases for the various techniques. Based on the results achieved in the current literature, we make recommendations on the appropriate architecture for a given task based on the number of channels and precision required, as well as the target fabric.

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A Review of New Time-to-Digital Conversion Techniques

During an at-speed scan-based test, excessive capture power may cause significant current demand, resulting in the IR-drop problem and unnecessary yield loss. Many methods address this problem by reducing the switching activities of power-risky patterns. These methods may not be efficient when the number of power-risky patterns is large or when some of the patterns require extremely high power. In this paper, we propose discarding all power-risky patterns and starting with power-safe patterns only. Our test generation procedure includes two processes, namely, test pattern refinement and low-power test pattern regeneration. The first process is used to refine the power-safe patterns to detect faults originally detected only by power-risky patterns. If some faults are still undetected after this process, the second process is applied to generate new power-safe patterns to detect these faults. The patterns obtained using the proposed procedure are guaranteed to be power-safe for the given power constraints. To the best of our knowledge, this is the first method that refines only the power-safe patterns to address the capture power problem. Experimental results on ISCAS'89 and ITC'99 benchmark circuits show that an average of 75% of faults originally detected only by power-risky patterns can be detected by refining power-safe patterns and that most of the remaining faults can be detected by the low-power test generation process. Furthermore, the required test data volume can be reduced by 12.76% on average with little or no fault coverage loss.

Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing

For two-pattern at-speed scan testing, the excessive power supply noise at the launch cycle may cause the circuit under test to malfunction, leading to yield loss. This paper proposes a new weight assignment scheme for logic switching activity; it enhances the IR-drop assessment capability of the existing weighted switching activity (WSA) model. By including the power grid network structure information, the proposed weight assignment better reflects the regional IR-drop impact of each switching event. For ATPG, such comprehensive information is crucial in determining whether a switching event burdens the IR-drop effect. Simulation results show that, compared with previous weight assignment schemes, the estimated regional IR-drop profiles better correlate with those generated by commercial tools.

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Improved weight assignment for logic switching activity during at-speed test pattern generation

At-speed or even faster-than-at-speed testing of VLSI circuits aims for high-quality screening of the circuits by targeting performance-related faults. On one hand, a compact test set with highly effective patterns, each detecting multiple delay faults, is desirable for lower test costs. On the other hand, such patterns increase switching activity during launch and capture operations. Patterns optimized for quality and cost may thus end up violating peak-power constraints, resulting in yield loss, while pattern generation under low switching activity constraints may lead to loss in test quality and/or pattern count inflation. In this paper, we propose design for testability (DfT) support for enabling the use of a set of patterns optimized for cost and quality as is, yet in a low power manner; we develop three different DfT mechanisms, one for launch-off shift, one for launch-off capture, and one for mixed at-speed testing. The proposed DfT support enables a design partitioning approach, where any given set of patterns, generated in a power-unaware manner, can be utilized to test the design regions one at a time, reducing both launch and capture power in a design-flow-compatible manner. This way, the test pattern count and quality of the optimized test set can be preserved, while lowering the launch/capture power.

Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing

Montgomery multiplication is the kernel operation in public key ciphers Aiming at parallel implementation of Montgomery multiplication, this brief presents an improved task partitioning of the Montgomery multiplication algorithm for the multicore platform with area-efficient processors Several multicore platforms are designed to verify the efficiency of parallelization The fastest platform takes 3460 cycles to finish a 1024-b Montgomery multiplication, which is six times faster than a single MIPS processor and three times faster than the pSHS parallelization based on a platform with eight MicroBlaze cores

Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform

Capture-safety, defined as the avoidance of any timing error due to unduly high launch switching activity in capture mode during at-speed scan testing, is critical for avoiding test- induced yield loss. Although point techniques are available for reducing capture IR-drop, there is a lack of complete capture-safe test generation flows. The paper addresses this problem by proposing a novel and practical capture-safe test generation scheme, featuring (1) reliable capture-safety checking and (2) effective capture-safety improvement by combining X-bit identification & X-filling with low launch- switching-activity test generation. This scheme is compatible with existing ATPG flows, and achieves capture-safety with no changes in the circuit-under-test or the clocking scheme.

A Capture-Safe Test Generation Scheme for At-Speed Scan Testing

This paper presents a time-to-digital converter (TDC) architecture with reduced hardware suitable for multichannel timing built-out self-test (BOST) implementation on an FPGA chip. In order to reduce the number of buffers and DFFs in a conventional Flash TDC or Vernier TDC, successive approximation is applied to construct a SAR TDC when two timing inputs are repetitive (not shingle-shot). Besides, Vernier TDC has been added as the sub-circuit to form a two-step SAR+SAR-Vernier TDC architecture. LTspice and Xilinx ISE simulation have been performed to verify its feasibility. Also discussions on several TDC architectures as BOST are described.

Successive approximation time-to-digital converter with vernier-level resolution

This paper introduces our production testing research results for analog and mixed-signal SoC in IoT era, such as operational amplifier, ADC, sampling circuit, timing related testing technologies. Notice that production testing and measurement / characterization for ICs are similar but different, and this paper introduces the former. The analog / mixed-signal testing plays a very important role in achieving both reliability and low cost for IoT and automotive systems. It also is a big technological challenge because there is no general method, but it requires state-of-the-art combination and optimization of a wide variety of technologies including circuit and system design as well as signal processing, control and measurement algorithms. Their overview including future technology challenges is described.

Analog/Mixed-Signal Circuit Testing Technologies in IoT Era

This paper describes algorithms and simulation verification of low-distortion sinusoidal signal generation methods with harmonics and image cancellation using an arbitrary waveform generator. We show high-frequency sinusoidal signal generation algorithms with HD3 image cancellation, HD3 & HD5 images cancellation, and point out that even harmonics images (such as HD2 image) is not required because they are far from the signal frequency. Also we show high-frequency two-tone signal generation with IMD3 suppression. With these methods, distortion components close to the signal are suppressed simply by changing the DSP program—AWG nonlinearity identification is not required—and spurious components, generated far from the signal band, are relatively easy to remove using an analog filter.

High-frequency low-distortion one-tone and two-tone signal generation using arbitrary waveform generator

In LSI testing, equivalent time sampling techniques are frequently used because the input signals to the device under test and the sampling clock are controllable; when the repetitive input signals are applied to the analog device under test, its output signals can be also repetitive. In this paper, we investigate an efficient waveform acquisition method with the equivalent-sampling using the metallic ratio of the sampling frequency and the input frequency, which is expected to be used for on-line, short-time and simple analog/RF/mixed-signal IC testing.

Kazumi Hatayama

Papers

A Capture-Safe Test Generation Scheme for At-Speed Scan Testing

Successive approximation time-to-digital converter with vernier-level resolution

Analog/Mixed-Signal Circuit Testing Technologies in IoT Era

High-frequency low-distortion one-tone and two-tone signal generation using arbitrary waveform generator

Metallic Ratio Equivalent-Time Sampling: A Highly Efficient Waveform Acquisition Method